文件名称:fpga_counter_Verilog
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- 上传时间:2015-11-23
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文件大小:208.64kb
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此文件是基于xilinx ise平台上开发的计数器,产生可调的脉冲,也可进行分频。-This document is based on xilinx ise platform counter, adjustable pulse generation, but also for the division.
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下载文件列表
fpga_counter_Verilog/a.vhd
fpga_counter_Verilog/counter.gise
fpga_counter_Verilog/counter.xise
fpga_counter_Verilog/counter3b.v
fpga_counter_Verilog/div_clk.cmd_log
fpga_counter_Verilog/div_clk.v
fpga_counter_Verilog/fuse.xmsgs
fpga_counter_Verilog/fuseRelaunch.cmd
fpga_counter_Verilog/iseconfig/counter.projectmgr
fpga_counter_Verilog/iseconfig/counter3b.xreport
fpga_counter_Verilog/iseconfig/top.xreport
fpga_counter_Verilog/pa.fromHdl.tcl
fpga_counter_Verilog/pa.fromNetlist.tcl
fpga_counter_Verilog/par_usage_statistics.html
fpga_counter_Verilog/planAhead.ngc2edif.log
fpga_counter_Verilog/planAhead_run_1/counter.data/cache/top_ngc_a2875f7e.edif
fpga_counter_Verilog/planAhead_run_1/counter.data/constrs_1/fileset.xml
fpga_counter_Verilog/planAhead_run_1/counter.data/runs/impl_1.psg
fpga_counter_Verilog/planAhead_run_1/counter.data/runs/runs.xml
fpga_counter_Verilog/planAhead_run_1/counter.data/sources_1/fileset.xml
fpga_counter_Verilog/planAhead_run_1/counter.data/wt/webtalk_pa.xml
fpga_counter_Verilog/planAhead_run_1/counter.ppr
fpga_counter_Verilog/planAhead_run_1/planAhead.jou
fpga_counter_Verilog/planAhead_run_1/planAhead.log
fpga_counter_Verilog/planAhead_run_1/planAhead_run.log
fpga_counter_Verilog/planAhead_run_2/counter.data/constrs_1/fileset.xml
fpga_counter_Verilog/planAhead_run_2/counter.data/sources_1/fileset.xml
fpga_counter_Verilog/planAhead_run_2/counter.data/wt/webtalk_pa.xml
fpga_counter_Verilog/planAhead_run_2/counter.ppr
fpga_counter_Verilog/planAhead_run_2/planAhead.jou
fpga_counter_Verilog/planAhead_run_2/planAhead.log
fpga_counter_Verilog/planAhead_run_2/planAhead_run.log
fpga_counter_Verilog/planAhead_run_3/planAhead.jou
fpga_counter_Verilog/planAhead_run_3/planAhead.log
fpga_counter_Verilog/planAhead_run_3/planAhead_run.log
fpga_counter_Verilog/planAhead_run_4/planAhead.jou
fpga_counter_Verilog/planAhead_run_4/planAhead.log
fpga_counter_Verilog/planAhead_run_4/planAhead_run.log
fpga_counter_Verilog/planAhead_run_5/planAhead.jou
fpga_counter_Verilog/planAhead_run_5/planAhead.log
fpga_counter_Verilog/planAhead_run_5/planAhead_run.log
fpga_counter_Verilog/test_counter.v
fpga_counter_Verilog/top.bgn
fpga_counter_Verilog/top.bit
fpga_counter_Verilog/top.bld
fpga_counter_Verilog/top.cdc
fpga_counter_Verilog/top.cmd_log
fpga_counter_Verilog/top.drc
fpga_counter_Verilog/top.lso
fpga_counter_Verilog/top.ncd
fpga_counter_Verilog/top.ngc
fpga_counter_Verilog/top.ngd
fpga_counter_Verilog/top.ngr
fpga_counter_Verilog/top.pad
fpga_counter_Verilog/top.par
fpga_counter_Verilog/top.pcf
fpga_counter_Verilog/top.prj
fpga_counter_Verilog/top.ptwx
fpga_counter_Verilog/top.spl
fpga_counter_Verilog/top.stx
fpga_counter_Verilog/top.sym
fpga_counter_Verilog/top.syr
fpga_counter_Verilog/top.tfi
fpga_counter_Verilog/top.twr
fpga_counter_Verilog/top.twx
fpga_counter_Verilog/top.ucf
fpga_counter_Verilog/top.unroutes
fpga_counter_Verilog/top.ut
fpga_counter_Verilog/top.v
fpga_counter_Verilog/top.xpi
fpga_counter_Verilog/top.xst
fpga_counter_Verilog/top_bitgen.xwbt
fpga_counter_Verilog/top_envsettings.html
fpga_counter_Verilog/top_guide.ncd
fpga_counter_Verilog/top_map.map
fpga_counter_Verilog/top_map.mrp
fpga_counter_Verilog/top_map.ncd
fpga_counter_Verilog/top_map.ngm
fpga_counter_Verilog/top_map.xrpt
fpga_counter_Verilog/top_ngdbuild.xrpt
fpga_counter_Verilog/top_pad.csv
fpga_counter_Verilog/top_pad.txt
fpga_counter_Verilog/top_par.xrpt
fpga_counter_Verilog/top_summary.html
fpga_counter_Verilog/top_summary.xml
fpga_counter_Verilog/top_usage.xml
fpga_counter_Verilog/top_xst.xrpt
fpga_counter_Verilog/usage_statistics_webtalk.html
fpga_counter_Verilog/webtalk.log
fpga_counter_Verilog/webtalk_pn.xml
fpga_counter_Verilog/xlnx_auto_0_xdb/cst.xbcd
fpga_counter_Verilog/xst/work/work.sdbl
fpga_counter_Verilog/xst/work/work.sdbx
fpga_counter_Verilog/_ngo/netlist.lst
fpga_counter_Verilog/_xmsgs/bitgen.xmsgs
fpga_counter_Verilog/_xmsgs/map.xmsgs
fpga_counter_Verilog/_xmsgs/ngdbuild.xmsgs
fpga_counter_Verilog/_xmsgs/par.xmsgs
fpga_counter_Verilog/_xmsgs/pn_parser.xmsgs
fpga_counter_Verilog/_xmsgs/trce.xmsgs
fpga_counter_Verilog/_xmsgs/xst.xmsgs
fpga_counter_Verilog/planAhead_run_1/counter.data/cache
fpga_counter_Verilog/planAhead_run_1/counter.data/constrs_1
fpga_counter_Verilog/planAhead_run_1/counter.data/runs
fpga_counter_Verilog/planAhead_run_1/counter.data/sources_1
fpga_counter_Verilog/planAhead_run_1/counter.data/wt
fpga_counter_Verilog/planAhead_run_2/counter.data/constrs_1
fpga_counter_Verilog/planAhead_run_2/counter.data/sources_1
fpga_counter_Verilog/planAhead_run_2/counter.data/wt
fpga_counter_Verilog/xst/dump.xst/top.prj
fpga_counter_Verilog/planAhead_run_1/counter.data
fpga_counter_Verilog/planAhead_run_2/counter.data
fpga_counter_Verilog/xst/dump.xst
fpga_counter_Verilog/xst/projnav.tmp
fpga_counter_Verilog/xst/work
fpga_counter_Verilog/ipcore_dir
fpga_counter_Verilog/iseconfig
fpga_counter_Verilog/planAhead_run_1
fpga_counter_Verilog/planAhead_run_2
fpga_counter_Verilog/planAhead_run_3
fpga_counter_Verilog/planAhead_run_4
fpga_counter_Verilog/planAhead_run_5
fpga_counter_Verilog/xlnx_auto_0_xdb
fpga_counter_Verilog/xst
fpga_cou
fpga_counter_Verilog/counter.gise
fpga_counter_Verilog/counter.xise
fpga_counter_Verilog/counter3b.v
fpga_counter_Verilog/div_clk.cmd_log
fpga_counter_Verilog/div_clk.v
fpga_counter_Verilog/fuse.xmsgs
fpga_counter_Verilog/fuseRelaunch.cmd
fpga_counter_Verilog/iseconfig/counter.projectmgr
fpga_counter_Verilog/iseconfig/counter3b.xreport
fpga_counter_Verilog/iseconfig/top.xreport
fpga_counter_Verilog/pa.fromHdl.tcl
fpga_counter_Verilog/pa.fromNetlist.tcl
fpga_counter_Verilog/par_usage_statistics.html
fpga_counter_Verilog/planAhead.ngc2edif.log
fpga_counter_Verilog/planAhead_run_1/counter.data/cache/top_ngc_a2875f7e.edif
fpga_counter_Verilog/planAhead_run_1/counter.data/constrs_1/fileset.xml
fpga_counter_Verilog/planAhead_run_1/counter.data/runs/impl_1.psg
fpga_counter_Verilog/planAhead_run_1/counter.data/runs/runs.xml
fpga_counter_Verilog/planAhead_run_1/counter.data/sources_1/fileset.xml
fpga_counter_Verilog/planAhead_run_1/counter.data/wt/webtalk_pa.xml
fpga_counter_Verilog/planAhead_run_1/counter.ppr
fpga_counter_Verilog/planAhead_run_1/planAhead.jou
fpga_counter_Verilog/planAhead_run_1/planAhead.log
fpga_counter_Verilog/planAhead_run_1/planAhead_run.log
fpga_counter_Verilog/planAhead_run_2/counter.data/constrs_1/fileset.xml
fpga_counter_Verilog/planAhead_run_2/counter.data/sources_1/fileset.xml
fpga_counter_Verilog/planAhead_run_2/counter.data/wt/webtalk_pa.xml
fpga_counter_Verilog/planAhead_run_2/counter.ppr
fpga_counter_Verilog/planAhead_run_2/planAhead.jou
fpga_counter_Verilog/planAhead_run_2/planAhead.log
fpga_counter_Verilog/planAhead_run_2/planAhead_run.log
fpga_counter_Verilog/planAhead_run_3/planAhead.jou
fpga_counter_Verilog/planAhead_run_3/planAhead.log
fpga_counter_Verilog/planAhead_run_3/planAhead_run.log
fpga_counter_Verilog/planAhead_run_4/planAhead.jou
fpga_counter_Verilog/planAhead_run_4/planAhead.log
fpga_counter_Verilog/planAhead_run_4/planAhead_run.log
fpga_counter_Verilog/planAhead_run_5/planAhead.jou
fpga_counter_Verilog/planAhead_run_5/planAhead.log
fpga_counter_Verilog/planAhead_run_5/planAhead_run.log
fpga_counter_Verilog/test_counter.v
fpga_counter_Verilog/top.bgn
fpga_counter_Verilog/top.bit
fpga_counter_Verilog/top.bld
fpga_counter_Verilog/top.cdc
fpga_counter_Verilog/top.cmd_log
fpga_counter_Verilog/top.drc
fpga_counter_Verilog/top.lso
fpga_counter_Verilog/top.ncd
fpga_counter_Verilog/top.ngc
fpga_counter_Verilog/top.ngd
fpga_counter_Verilog/top.ngr
fpga_counter_Verilog/top.pad
fpga_counter_Verilog/top.par
fpga_counter_Verilog/top.pcf
fpga_counter_Verilog/top.prj
fpga_counter_Verilog/top.ptwx
fpga_counter_Verilog/top.spl
fpga_counter_Verilog/top.stx
fpga_counter_Verilog/top.sym
fpga_counter_Verilog/top.syr
fpga_counter_Verilog/top.tfi
fpga_counter_Verilog/top.twr
fpga_counter_Verilog/top.twx
fpga_counter_Verilog/top.ucf
fpga_counter_Verilog/top.unroutes
fpga_counter_Verilog/top.ut
fpga_counter_Verilog/top.v
fpga_counter_Verilog/top.xpi
fpga_counter_Verilog/top.xst
fpga_counter_Verilog/top_bitgen.xwbt
fpga_counter_Verilog/top_envsettings.html
fpga_counter_Verilog/top_guide.ncd
fpga_counter_Verilog/top_map.map
fpga_counter_Verilog/top_map.mrp
fpga_counter_Verilog/top_map.ncd
fpga_counter_Verilog/top_map.ngm
fpga_counter_Verilog/top_map.xrpt
fpga_counter_Verilog/top_ngdbuild.xrpt
fpga_counter_Verilog/top_pad.csv
fpga_counter_Verilog/top_pad.txt
fpga_counter_Verilog/top_par.xrpt
fpga_counter_Verilog/top_summary.html
fpga_counter_Verilog/top_summary.xml
fpga_counter_Verilog/top_usage.xml
fpga_counter_Verilog/top_xst.xrpt
fpga_counter_Verilog/usage_statistics_webtalk.html
fpga_counter_Verilog/webtalk.log
fpga_counter_Verilog/webtalk_pn.xml
fpga_counter_Verilog/xlnx_auto_0_xdb/cst.xbcd
fpga_counter_Verilog/xst/work/work.sdbl
fpga_counter_Verilog/xst/work/work.sdbx
fpga_counter_Verilog/_ngo/netlist.lst
fpga_counter_Verilog/_xmsgs/bitgen.xmsgs
fpga_counter_Verilog/_xmsgs/map.xmsgs
fpga_counter_Verilog/_xmsgs/ngdbuild.xmsgs
fpga_counter_Verilog/_xmsgs/par.xmsgs
fpga_counter_Verilog/_xmsgs/pn_parser.xmsgs
fpga_counter_Verilog/_xmsgs/trce.xmsgs
fpga_counter_Verilog/_xmsgs/xst.xmsgs
fpga_counter_Verilog/planAhead_run_1/counter.data/cache
fpga_counter_Verilog/planAhead_run_1/counter.data/constrs_1
fpga_counter_Verilog/planAhead_run_1/counter.data/runs
fpga_counter_Verilog/planAhead_run_1/counter.data/sources_1
fpga_counter_Verilog/planAhead_run_1/counter.data/wt
fpga_counter_Verilog/planAhead_run_2/counter.data/constrs_1
fpga_counter_Verilog/planAhead_run_2/counter.data/sources_1
fpga_counter_Verilog/planAhead_run_2/counter.data/wt
fpga_counter_Verilog/xst/dump.xst/top.prj
fpga_counter_Verilog/planAhead_run_1/counter.data
fpga_counter_Verilog/planAhead_run_2/counter.data
fpga_counter_Verilog/xst/dump.xst
fpga_counter_Verilog/xst/projnav.tmp
fpga_counter_Verilog/xst/work
fpga_counter_Verilog/ipcore_dir
fpga_counter_Verilog/iseconfig
fpga_counter_Verilog/planAhead_run_1
fpga_counter_Verilog/planAhead_run_2
fpga_counter_Verilog/planAhead_run_3
fpga_counter_Verilog/planAhead_run_4
fpga_counter_Verilog/planAhead_run_5
fpga_counter_Verilog/xlnx_auto_0_xdb
fpga_counter_Verilog/xst
fpga_cou
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