8 位串入、并出移位寄存器，时钟上升沿数据右移一位，输入为DSA和DSB的逻辑与。复位端低有效，非同步地清除寄存器，强制所有的输出为低电平。-8 string into and out of the shift register, the clock rising edge of data to the right one, input logic and DSA and DSB. Active low reset terminal, non-synchronously cleared register, forces all of the output is low.