文件名称:cpu_me
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- 上传时间:2015-12-10
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文件大小:66.66kb
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已下载:0次
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采用verilog编写的cpu,modelsim仿真均实现8条指令功能,有虚拟ram和rom-Using verilog prepared cpu, modelsim simulation functions are to achieve eight instructions, there are virtual ram and rom
(系统自动生成,下载前可以参看下载内容)
下载文件列表
cpu_me/accum.v
cpu_me/adr.v
cpu_me/alu.v
cpu_me/alu.v.bak
cpu_me/clk_gen.v
cpu_me/counter.v
cpu_me/cpu_me.cr.mti
cpu_me/cpu_me.mpf
cpu_me/cpu_top.v
cpu_me/datactl.v
cpu_me/ram.dat
cpu_me/ram.v
cpu_me/ram.v.bak
cpu_me/register.v
cpu_me/rom.dat
cpu_me/rom.v
cpu_me/rom.v.bak
cpu_me/state_machie.v
cpu_me/state_machie.v.bak
cpu_me/tcl_stacktrace.txt
cpu_me/top_tb.v
cpu_me/top_tb.v.bak
cpu_me/transcript
cpu_me/vsim.wlf
cpu_me/work/accum/verilog.prw
cpu_me/work/accum/verilog.psm
cpu_me/work/accum/_primary.dat
cpu_me/work/accum/_primary.dbs
cpu_me/work/accum/_primary.vhd
cpu_me/work/adr/verilog.prw
cpu_me/work/adr/verilog.psm
cpu_me/work/adr/_primary.dat
cpu_me/work/adr/_primary.dbs
cpu_me/work/adr/_primary.vhd
cpu_me/work/alu/verilog.prw
cpu_me/work/alu/verilog.psm
cpu_me/work/alu/_primary.dat
cpu_me/work/alu/_primary.dbs
cpu_me/work/alu/_primary.vhd
cpu_me/work/clk_gen/verilog.prw
cpu_me/work/clk_gen/verilog.psm
cpu_me/work/clk_gen/_primary.dat
cpu_me/work/clk_gen/_primary.dbs
cpu_me/work/clk_gen/_primary.vhd
cpu_me/work/counter/verilog.prw
cpu_me/work/counter/verilog.psm
cpu_me/work/counter/_primary.dat
cpu_me/work/counter/_primary.dbs
cpu_me/work/counter/_primary.vhd
cpu_me/work/cpu_top/verilog.prw
cpu_me/work/cpu_top/verilog.psm
cpu_me/work/cpu_top/_primary.dat
cpu_me/work/cpu_top/_primary.dbs
cpu_me/work/cpu_top/_primary.vhd
cpu_me/work/datactl/verilog.prw
cpu_me/work/datactl/verilog.psm
cpu_me/work/datactl/_primary.dat
cpu_me/work/datactl/_primary.dbs
cpu_me/work/datactl/_primary.vhd
cpu_me/work/ram/verilog.prw
cpu_me/work/ram/verilog.psm
cpu_me/work/ram/_primary.dat
cpu_me/work/ram/_primary.dbs
cpu_me/work/ram/_primary.vhd
cpu_me/work/register/verilog.prw
cpu_me/work/register/verilog.psm
cpu_me/work/register/_primary.dat
cpu_me/work/register/_primary.dbs
cpu_me/work/register/_primary.vhd
cpu_me/work/rom/verilog.prw
cpu_me/work/rom/verilog.psm
cpu_me/work/rom/_primary.dat
cpu_me/work/rom/_primary.dbs
cpu_me/work/rom/_primary.vhd
cpu_me/work/state_machie/verilog.prw
cpu_me/work/state_machie/verilog.psm
cpu_me/work/state_machie/_primary.dat
cpu_me/work/state_machie/_primary.dbs
cpu_me/work/state_machie/_primary.vhd
cpu_me/work/top_tb/verilog.prw
cpu_me/work/top_tb/verilog.psm
cpu_me/work/top_tb/_primary.dat
cpu_me/work/top_tb/_primary.dbs
cpu_me/work/top_tb/_primary.vhd
cpu_me/work/_info
cpu_me/work/_vmake
cpu_me/work/accum
cpu_me/work/adr
cpu_me/work/alu
cpu_me/work/clk_gen
cpu_me/work/counter
cpu_me/work/cpu_top
cpu_me/work/datactl
cpu_me/work/ram
cpu_me/work/register
cpu_me/work/rom
cpu_me/work/state_machie
cpu_me/work/top_tb
cpu_me/work/_temp
cpu_me/work
cpu_me
cpu_me/adr.v
cpu_me/alu.v
cpu_me/alu.v.bak
cpu_me/clk_gen.v
cpu_me/counter.v
cpu_me/cpu_me.cr.mti
cpu_me/cpu_me.mpf
cpu_me/cpu_top.v
cpu_me/datactl.v
cpu_me/ram.dat
cpu_me/ram.v
cpu_me/ram.v.bak
cpu_me/register.v
cpu_me/rom.dat
cpu_me/rom.v
cpu_me/rom.v.bak
cpu_me/state_machie.v
cpu_me/state_machie.v.bak
cpu_me/tcl_stacktrace.txt
cpu_me/top_tb.v
cpu_me/top_tb.v.bak
cpu_me/transcript
cpu_me/vsim.wlf
cpu_me/work/accum/verilog.prw
cpu_me/work/accum/verilog.psm
cpu_me/work/accum/_primary.dat
cpu_me/work/accum/_primary.dbs
cpu_me/work/accum/_primary.vhd
cpu_me/work/adr/verilog.prw
cpu_me/work/adr/verilog.psm
cpu_me/work/adr/_primary.dat
cpu_me/work/adr/_primary.dbs
cpu_me/work/adr/_primary.vhd
cpu_me/work/alu/verilog.prw
cpu_me/work/alu/verilog.psm
cpu_me/work/alu/_primary.dat
cpu_me/work/alu/_primary.dbs
cpu_me/work/alu/_primary.vhd
cpu_me/work/clk_gen/verilog.prw
cpu_me/work/clk_gen/verilog.psm
cpu_me/work/clk_gen/_primary.dat
cpu_me/work/clk_gen/_primary.dbs
cpu_me/work/clk_gen/_primary.vhd
cpu_me/work/counter/verilog.prw
cpu_me/work/counter/verilog.psm
cpu_me/work/counter/_primary.dat
cpu_me/work/counter/_primary.dbs
cpu_me/work/counter/_primary.vhd
cpu_me/work/cpu_top/verilog.prw
cpu_me/work/cpu_top/verilog.psm
cpu_me/work/cpu_top/_primary.dat
cpu_me/work/cpu_top/_primary.dbs
cpu_me/work/cpu_top/_primary.vhd
cpu_me/work/datactl/verilog.prw
cpu_me/work/datactl/verilog.psm
cpu_me/work/datactl/_primary.dat
cpu_me/work/datactl/_primary.dbs
cpu_me/work/datactl/_primary.vhd
cpu_me/work/ram/verilog.prw
cpu_me/work/ram/verilog.psm
cpu_me/work/ram/_primary.dat
cpu_me/work/ram/_primary.dbs
cpu_me/work/ram/_primary.vhd
cpu_me/work/register/verilog.prw
cpu_me/work/register/verilog.psm
cpu_me/work/register/_primary.dat
cpu_me/work/register/_primary.dbs
cpu_me/work/register/_primary.vhd
cpu_me/work/rom/verilog.prw
cpu_me/work/rom/verilog.psm
cpu_me/work/rom/_primary.dat
cpu_me/work/rom/_primary.dbs
cpu_me/work/rom/_primary.vhd
cpu_me/work/state_machie/verilog.prw
cpu_me/work/state_machie/verilog.psm
cpu_me/work/state_machie/_primary.dat
cpu_me/work/state_machie/_primary.dbs
cpu_me/work/state_machie/_primary.vhd
cpu_me/work/top_tb/verilog.prw
cpu_me/work/top_tb/verilog.psm
cpu_me/work/top_tb/_primary.dat
cpu_me/work/top_tb/_primary.dbs
cpu_me/work/top_tb/_primary.vhd
cpu_me/work/_info
cpu_me/work/_vmake
cpu_me/work/accum
cpu_me/work/adr
cpu_me/work/alu
cpu_me/work/clk_gen
cpu_me/work/counter
cpu_me/work/cpu_top
cpu_me/work/datactl
cpu_me/work/ram
cpu_me/work/register
cpu_me/work/rom
cpu_me/work/state_machie
cpu_me/work/top_tb
cpu_me/work/_temp
cpu_me/work
cpu_me
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