文件名称:DES_verilog
-
所属分类:
- 标签属性:
- 上传时间:2015-12-24
-
文件大小:465.57kb
-
已下载:0次
-
提 供 者:
-
相关连接:无下载说明:别用迅雷下载,失败请重下,重下不扣分!
介绍说明--下载内容来自于网络,使用问题请自行百度
用verilog实现的DES(Data Encryption Standard数据加密标准),把64位明文输入变为64位密文输出块。-Using DES (Data Encryption Standard Data Encryption Standard) verilog to achieve, the 64 plaintext input into 64 output ciphertext block.
(系统自动生成,下载前可以参看下载内容)
下载文件列表
11.1/
11.1/chart/
11.1/chart/Thumbs.db
11.1/chart/图11-12.bmp
11.1/chart/图11-13.bmp
11.1/chart/图11-14.bmp
11.1/chart/图11-15.bmp
11.1/chart/图11-16.bmp
11.1/chart/图11-19.bmp
11.1/chart/图11-20.bmp
11.1/chart/图11-5.bmp
11.1/chart/图11-6.bmp
11.1/chart/图11-8.bmp
11.1/chart/图11-9.bmp
11.1/chart/表11-1.bmp
11.1/chart/表11-2.bmp
11.1/chart/表11-3.bmp
11.1/chart/表11-4.bmp
11.1/chart/表11-5.bmp
11.1/chart/表11-6.bmp
11.1/chart/表11-8.bmp
11.1/chart/表11-9.bmp
11.1/des.cr.mti
11.1/des.mpf
11.1/des.v
11.1/des_testbench.v
11.1/desround.v
11.1/key_gen.v
11.1/s1.v
11.1/s2.v
11.1/s3.v
11.1/s4.v
11.1/s5.v
11.1/s6.v
11.1/s7.v
11.1/s8.v
11.1/transcript
11.1/vsim.wlf
11.1/wave/
11.1/wave/Thumbs.db
11.1/wave/des.bmp
11.1/wave/des_testbench.bmp
11.1/wave/desround.bmp
11.1/wave/key_gen.bmp
11.1/wave/s1~s8.bmp
11.1/wb_descontroller.v
11.1/work/
11.1/work/_info
11.1/work/des/
11.1/work/des/_primary.dat
11.1/work/des/_primary.vhd
11.1/work/des/verilog.asm
11.1/work/des_testbench/
11.1/work/des_testbench/_primary.dat
11.1/work/des_testbench/_primary.vhd
11.1/work/des_testbench/verilog.asm
11.1/work/des_top/
11.1/work/des_top/_primary.dat
11.1/work/des_top/_primary.vhd
11.1/work/des_top/verilog.asm
11.1/work/desround/
11.1/work/desround/_primary.dat
11.1/work/desround/_primary.vhd
11.1/work/desround/verilog.asm
11.1/work/key_gen/
11.1/work/key_gen/_primary.dat
11.1/work/key_gen/_primary.vhd
11.1/work/key_gen/verilog.asm
11.1/work/s1/
11.1/work/s1/_primary.dat
11.1/work/s1/_primary.vhd
11.1/work/s1/verilog.asm
11.1/work/s2/
11.1/work/s2/_primary.dat
11.1/work/s2/_primary.vhd
11.1/work/s2/verilog.asm
11.1/work/s3/
11.1/work/s3/_primary.dat
11.1/work/s3/_primary.vhd
11.1/work/s3/verilog.asm
11.1/work/s4/
11.1/work/s4/_primary.dat
11.1/work/s4/_primary.vhd
11.1/work/s4/verilog.asm
11.1/work/s5/
11.1/work/s5/_primary.dat
11.1/work/s5/_primary.vhd
11.1/work/s5/verilog.asm
11.1/work/s6/
11.1/work/s6/_primary.dat
11.1/work/s6/_primary.vhd
11.1/work/s6/verilog.asm
11.1/work/s7/
11.1/work/s7/_primary.dat
11.1/work/s7/_primary.vhd
11.1/work/s7/verilog.asm
11.1/work/s8/
11.1/work/s8/_primary.dat
11.1/work/s8/_primary.vhd
11.1/work/s8/verilog.asm
11.1/work/top/
11.1/work/top/_primary.dat
11.1/work/top/_primary.vhd
11.1/work/top/verilog.asm
11.1/chart/
11.1/chart/Thumbs.db
11.1/chart/图11-12.bmp
11.1/chart/图11-13.bmp
11.1/chart/图11-14.bmp
11.1/chart/图11-15.bmp
11.1/chart/图11-16.bmp
11.1/chart/图11-19.bmp
11.1/chart/图11-20.bmp
11.1/chart/图11-5.bmp
11.1/chart/图11-6.bmp
11.1/chart/图11-8.bmp
11.1/chart/图11-9.bmp
11.1/chart/表11-1.bmp
11.1/chart/表11-2.bmp
11.1/chart/表11-3.bmp
11.1/chart/表11-4.bmp
11.1/chart/表11-5.bmp
11.1/chart/表11-6.bmp
11.1/chart/表11-8.bmp
11.1/chart/表11-9.bmp
11.1/des.cr.mti
11.1/des.mpf
11.1/des.v
11.1/des_testbench.v
11.1/desround.v
11.1/key_gen.v
11.1/s1.v
11.1/s2.v
11.1/s3.v
11.1/s4.v
11.1/s5.v
11.1/s6.v
11.1/s7.v
11.1/s8.v
11.1/transcript
11.1/vsim.wlf
11.1/wave/
11.1/wave/Thumbs.db
11.1/wave/des.bmp
11.1/wave/des_testbench.bmp
11.1/wave/desround.bmp
11.1/wave/key_gen.bmp
11.1/wave/s1~s8.bmp
11.1/wb_descontroller.v
11.1/work/
11.1/work/_info
11.1/work/des/
11.1/work/des/_primary.dat
11.1/work/des/_primary.vhd
11.1/work/des/verilog.asm
11.1/work/des_testbench/
11.1/work/des_testbench/_primary.dat
11.1/work/des_testbench/_primary.vhd
11.1/work/des_testbench/verilog.asm
11.1/work/des_top/
11.1/work/des_top/_primary.dat
11.1/work/des_top/_primary.vhd
11.1/work/des_top/verilog.asm
11.1/work/desround/
11.1/work/desround/_primary.dat
11.1/work/desround/_primary.vhd
11.1/work/desround/verilog.asm
11.1/work/key_gen/
11.1/work/key_gen/_primary.dat
11.1/work/key_gen/_primary.vhd
11.1/work/key_gen/verilog.asm
11.1/work/s1/
11.1/work/s1/_primary.dat
11.1/work/s1/_primary.vhd
11.1/work/s1/verilog.asm
11.1/work/s2/
11.1/work/s2/_primary.dat
11.1/work/s2/_primary.vhd
11.1/work/s2/verilog.asm
11.1/work/s3/
11.1/work/s3/_primary.dat
11.1/work/s3/_primary.vhd
11.1/work/s3/verilog.asm
11.1/work/s4/
11.1/work/s4/_primary.dat
11.1/work/s4/_primary.vhd
11.1/work/s4/verilog.asm
11.1/work/s5/
11.1/work/s5/_primary.dat
11.1/work/s5/_primary.vhd
11.1/work/s5/verilog.asm
11.1/work/s6/
11.1/work/s6/_primary.dat
11.1/work/s6/_primary.vhd
11.1/work/s6/verilog.asm
11.1/work/s7/
11.1/work/s7/_primary.dat
11.1/work/s7/_primary.vhd
11.1/work/s7/verilog.asm
11.1/work/s8/
11.1/work/s8/_primary.dat
11.1/work/s8/_primary.vhd
11.1/work/s8/verilog.asm
11.1/work/top/
11.1/work/top/_primary.dat
11.1/work/top/_primary.vhd
11.1/work/top/verilog.asm
本网站为编程资源及源代码搜集、介绍的搜索网站,版权归原作者所有! 粤ICP备11031372号
1999-2046 搜珍网 All Rights Reserved.