oc-i2c-master/
oc-i2c-master/README.textile
oc-i2c-master/bench/
oc-i2c-master/bench/verilog/
oc-i2c-master/bench/verilog/i2c_slave_model.v
oc-i2c-master/bench/verilog/spi_slave_model.v
oc-i2c-master/bench/verilog/tst_bench_top.v
oc-i2c-master/bench/verilog/wb_master_model.v
oc-i2c-master/doc/
oc-i2c-master/doc/i2c_specs.pdf
oc-i2c-master/doc/src/
oc-i2c-master/doc/src/I2C_specs.doc
oc-i2c-master/rtl/
oc-i2c-master/rtl/verilog/
oc-i2c-master/rtl/verilog/i2c_master_bit_ctrl.v
oc-i2c-master/rtl/verilog/i2c_master_byte_ctrl.v
oc-i2c-master/rtl/verilog/i2c_master_defines.v
oc-i2c-master/rtl/verilog/i2c_master_top.v
oc-i2c-master/rtl/verilog/timescale.v
oc-i2c-master/rtl/vhdl/
oc-i2c-master/rtl/vhdl/I2C.VHD
oc-i2c-master/rtl/vhdl/i2c_master_avalon.vhd
oc-i2c-master/rtl/vhdl/i2c_master_avalon_hw.tcl
oc-i2c-master/rtl/vhdl/i2c_master_bit_ctrl.vhd
oc-i2c-master/rtl/vhdl/i2c_master_byte_ctrl.vhd
oc-i2c-master/rtl/vhdl/i2c_master_top.vhd
oc-i2c-master/rtl/vhdl/readme
oc-i2c-master/rtl/vhdl/tst_ds1621.vhd
oc-i2c-master/sim/
oc-i2c-master/sim/i2c_verilog/
oc-i2c-master/sim/i2c_verilog/run/
oc-i2c-master/sim/i2c_verilog/run/bench.vcd
oc-i2c-master/sim/i2c_verilog/run/ncverilog.key
oc-i2c-master/sim/i2c_verilog/run/ncverilog.log
oc-i2c-master/sim/i2c_verilog/run/run
oc-i2c-master/software/
oc-i2c-master/software/include/
oc-i2c-master/software/include/oc_i2c_master.h