文件名称:Asy_slavefifo_rdwr(141027)
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FPGA 控制CY7C68013A芯片的收发程序,调试通过,最高速度18M-CY7C68013A chip transceiver FPGA control procedures, debugging through, the maximum speed of 18M
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Asy_slavefifo_rdwr(141027)/
Asy_slavefifo_rdwr(141027)/Asy_slavefifo.bsf
Asy_slavefifo_rdwr(141027)/Asy_slavefifo.qar
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Asy_slavefifo_rdwr(141027)/Asy_slavefifo.qsf
Asy_slavefifo_rdwr(141027)/Asy_slavefifo.qws
Asy_slavefifo_rdwr(141027)/Asy_slavefifo.v
Asy_slavefifo_rdwr(141027)/Asy_slavefifo.v.bak
Asy_slavefifo_rdwr(141027)/PLL.bsf
Asy_slavefifo_rdwr(141027)/PLL.cmp
Asy_slavefifo_rdwr(141027)/PLL.ppf
Asy_slavefifo_rdwr(141027)/PLL.qip
Asy_slavefifo_rdwr(141027)/PLL.vhd
Asy_slavefifo_rdwr(141027)/PLLJ_PLLSPE_INFO.txt
Asy_slavefifo_rdwr(141027)/Reset.bsf
Asy_slavefifo_rdwr(141027)/Reset.v
Asy_slavefifo_rdwr(141027)/TOP.bdf
Asy_slavefifo_rdwr(141027)/db/
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Asy_slavefifo_rdwr(141027)/db/Asy_
Asy_slavefifo_rdwr(141027)/Asy_slavefifo.bsf
Asy_slavefifo_rdwr(141027)/Asy_slavefifo.qar
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Asy_slavefifo_rdwr(141027)/Asy_slavefifo.qsf
Asy_slavefifo_rdwr(141027)/Asy_slavefifo.qws
Asy_slavefifo_rdwr(141027)/Asy_slavefifo.v
Asy_slavefifo_rdwr(141027)/Asy_slavefifo.v.bak
Asy_slavefifo_rdwr(141027)/PLL.bsf
Asy_slavefifo_rdwr(141027)/PLL.cmp
Asy_slavefifo_rdwr(141027)/PLL.ppf
Asy_slavefifo_rdwr(141027)/PLL.qip
Asy_slavefifo_rdwr(141027)/PLL.vhd
Asy_slavefifo_rdwr(141027)/PLLJ_PLLSPE_INFO.txt
Asy_slavefifo_rdwr(141027)/Reset.bsf
Asy_slavefifo_rdwr(141027)/Reset.v
Asy_slavefifo_rdwr(141027)/TOP.bdf
Asy_slavefifo_rdwr(141027)/db/
Asy_slavefifo_rdwr(141027)/db/Asy_slavefifo.(0).cnf.cdb
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Asy_slavefifo_rdwr(141027)/db/Asy_
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