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文件名称:uart16550.tar

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    2016-02-05
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    239.6kb
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UART Verilog RTL Code
(系统自动生成,下载前可以参看下载内容)

下载文件列表

uart16550/
uart16550/CVS/
uart16550/CVS/Root
uart16550/CVS/Repository
uart16550/CVS/Entries
uart16550/Doc/
uart16550/Doc/CVS/
uart16550/Doc/CVS/Root
uart16550/Doc/CVS/Repository
uart16550/Doc/CVS/Entries
uart16550/bench/
uart16550/bench/CVS/
uart16550/bench/CVS/Root
uart16550/bench/CVS/Repository
uart16550/bench/CVS/Entries
uart16550/bench/verilog/
uart16550/bench/verilog/CVS/
uart16550/bench/verilog/CVS/Root
uart16550/bench/verilog/CVS/Repository
uart16550/bench/verilog/CVS/Entries
uart16550/bench/verilog/readme.txt
uart16550/bench/verilog/uart_device.v
uart16550/bench/verilog/uart_device_utilities.v
uart16550/bench/verilog/uart_log.v
uart16550/bench/verilog/uart_test.v
uart16550/bench/verilog/uart_testbench.v
uart16550/bench/verilog/uart_testbench_defines.v
uart16550/bench/verilog/uart_testbench_utilities.v
uart16550/bench/verilog/uart_wb_utilities.v
uart16550/bench/verilog/vapi.log
uart16550/bench/verilog/wb_mast.v
uart16550/bench/verilog/wb_master_model.v
uart16550/bench/verilog/wb_model_defines.v
uart16550/bench/verilog/test_cases/
uart16550/bench/verilog/test_cases/CVS/
uart16550/bench/verilog/test_cases/CVS/Root
uart16550/bench/verilog/test_cases/CVS/Repository
uart16550/bench/verilog/test_cases/CVS/Entries
uart16550/bench/verilog/test_cases/uart_int.v
uart16550/bench/vhdl/
uart16550/bench/vhdl/CVS/
uart16550/bench/vhdl/CVS/Root
uart16550/bench/vhdl/CVS/Repository
uart16550/bench/vhdl/CVS/Entries
uart16550/bench/vhdl/.keepme
uart16550/doc/
uart16550/doc/CVS/
uart16550/doc/CVS/Root
uart16550/doc/CVS/Repository
uart16550/doc/CVS/Entries
uart16550/doc/CHANGES.txt
uart16550/doc/UART_spec.pdf
uart16550/doc/src/
uart16550/doc/src/CVS/
uart16550/doc/src/CVS/Root
uart16550/doc/src/CVS/Repository
uart16550/doc/src/CVS/Entries
uart16550/doc/src/UART_spec.doc
uart16550/fv/
uart16550/fv/CVS/
uart16550/fv/CVS/Root
uart16550/fv/CVS/Repository
uart16550/fv/CVS/Entries
uart16550/fv/.keepme
uart16550/lint/
uart16550/lint/CVS/
uart16550/lint/CVS/Root
uart16550/lint/CVS/Repository
uart16550/lint/CVS/Entries
uart16550/lint/bin/
uart16550/lint/bin/CVS/
uart16550/lint/bin/CVS/Root
uart16550/lint/bin/CVS/Repository
uart16550/lint/bin/CVS/Entries
uart16550/lint/bin/.keepme
uart16550/lint/log/
uart16550/lint/log/CVS/
uart16550/lint/log/CVS/Root
uart16550/lint/log/CVS/Repository
uart16550/lint/log/CVS/Entries
uart16550/lint/log/.keepme
uart16550/lint/out/
uart16550/lint/out/CVS/
uart16550/lint/out/CVS/Root
uart16550/lint/out/CVS/Repository
uart16550/lint/out/CVS/Entries
uart16550/lint/out/.keepme
uart16550/lint/run/
uart16550/lint/run/CVS/
uart16550/lint/run/CVS/Root
uart16550/lint/run/CVS/Repository
uart16550/lint/run/CVS/Entries
uart16550/lint/run/.keepme
uart16550/rtl/
uart16550/rtl/CVS/
uart16550/rtl/CVS/Root
uart16550/rtl/CVS/Repository
uart16550/rtl/CVS/Entries
uart16550/rtl/verilog/
uart16550/rtl/verilog/CVS/
uart16550/rtl/verilog/CVS/Root
uart16550/rtl/verilog/CVS/Repository
uart16550/rtl/verilog/CVS/Entries
uart16550/rtl/verilog/raminfr.v
uart16550/rtl/verilog/timescale.v
uart16550/rtl/verilog/uart_debug_if.v
uart16550/rtl/verilog/uart_defines.v
uart16550/rtl/verilog/uart_receiver.v
uart16550/rtl/verilog/uart_regs.v
uart16550/rtl/verilog/uart_rfifo.v
uart16550/rtl/verilog/uart_sync_flops.v
uart16550/rtl/verilog/uart_tfifo.v
uart16550/rtl/verilog/uart_top.v
uart16550/rtl/verilog/uart_transmitter.v
uart16550/rtl/verilog/uart_wb.v
uart16550/rtl/verilog-backup/
uart16550/rtl/verilog-backup/CVS/
uart16550/rtl/verilog-backup/CVS/Root
uart16550/rtl/verilog-backup/CVS/Repository
uart16550/rtl/verilog-backup/CVS/Entries
uart16550/rtl/verilog-backup/timescale.v
uart16550/rtl/verilog-backup/uart_defines.v
uart16550/rtl/verilog-backup/uart_fifo.v
uart16550/rtl/verilog-backup/uart_receiver.v
uart16550/rtl/verilog-backup/uart_regs.v
uart16550/rtl/verilog-backup/uart_top.v
uart16550/rtl/verilog-backup/uart_transmitter.v
uart16550/rtl/verilog-backup/uart_wb.v
uart16550/rtl/vhdl/
uart16550/rtl/vhdl/CVS/
uart16550/rtl/vhdl/CVS/Root
uart16550/rtl/vhdl/CVS/Repository
uart16550/rtl/vhdl/CVS/Entries
uart16550/rtl/vhdl/.keepme
uart16550/sim/
uart16550/sim/CVS/
uart16550/sim/CVS/Root
uart16550/sim/CVS/Repository
uart16550/sim/CVS/Entries
uart16550/sim/gate_sim/
uart16550/sim/gate_sim/CVS/
uart16550/sim/gate_sim/CVS/Root
uart16550/sim/gate_sim/CVS/Repository
uart16550/sim/gate_sim/CVS/Entries
uart16550/sim/gate_sim/bin/
uart16550/sim/gate_sim/bin/CVS/
uart16550/sim/gate_sim/bin/CVS/Root
uart16550/sim/gate_sim/bin/CVS/Repository
uart16550/sim/gate_sim/bin/CVS/Entries
uart16550/sim/gate_sim/bin/.keepme
uart16550/sim/gate_sim/log/
uart16550/sim/gate_sim/log/CVS/
uart16550/sim/gate_sim/log/CVS/Root
uart16550/sim/gate_sim/log/CVS/Repository
uart16550/sim/gate_sim/log/CVS/Entries
uart16550/sim/gate_sim/log/.keepme
uart16550/sim/gate_sim/out/
uart16550/sim/gate_sim/out/CVS/
uart16550/sim/gate_sim/out/CVS/Root
uart16550/sim/gate_sim/out/CVS/Repository
uart16550/sim/gate_sim/out/CVS/Entries
uart16550/sim/gate_sim/out/.keepme
uart16550/sim/gate_sim/run/
uart16550/sim/gate_sim/run/CVS/
uart16550/sim/gate_sim/run/CVS/Root
uart16550/sim/gate_sim/run/CVS/Repository
uart165

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