文件名称:m-sequence_gen
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文件大小:226.78kb
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m序列生成verilog代码,经过仿真测试,绝对可用,带仿真说明-M sequence generated Verilog code, after the simulation test, absolutely available, with the simulation
(系统自动生成,下载前可以参看下载内容)
下载文件列表
m-sequence_gen/rtl/control.v
m-sequence_gen/rtl/lfsr.v
m-sequence_gen/rtl/rom.v
m-sequence_gen/rtl/sr.v
m-sequence_gen/sim/sim.tcl
m-sequence_gen/sim/transcript
m-sequence_gen/sim/vsim.wlf
m-sequence_gen/sim/work/@_opt/vopt229biv
m-sequence_gen/sim/work/@_opt/vopt2sctj2
m-sequence_gen/sim/work/@_opt/vopt3rgjet
m-sequence_gen/sim/work/@_opt/vopt4r64gj
m-sequence_gen/sim/work/@_opt/vopt592nj2
m-sequence_gen/sim/work/@_opt/vopt6iy8iv
m-sequence_gen/sim/work/@_opt/vopt786get
m-sequence_gen/sim/work/@_opt/vopt88w1gj
m-sequence_gen/sim/work/@_opt/vopt92k5iv
m-sequence_gen/sim/work/@_opt/vopt9sqjj2
m-sequence_gen/sim/work/@_opt/voptafvdht
m-sequence_gen/sim/work/@_opt/voptbrhxfj
m-sequence_gen/sim/work/@_opt/voptc9dgj2
m-sequence_gen/sim/work/@_opt/voptdhb1xt
m-sequence_gen/sim/work/@_opt/voptezg9ht
m-sequence_gen/sim/work/@_opt/voptfz6tij
m-sequence_gen/sim/work/@_opt/voptgr0yzt
m-sequence_gen/sim/work/@_opt/voptgs2dj2
m-sequence_gen/sim/work/@_opt/vopthf66ht
m-sequence_gen/sim/work/@_opt/voptk3nygv
m-sequence_gen/sim/work/@_opt/voptk8nvzt
m-sequence_gen/sim/work/@_opt/voptk8t9y1
m-sequence_gen/sim/work/@_opt/voptndihyi
m-sequence_gen/sim/work/@_opt/voptqrbrzt
m-sequence_gen/sim/work/@_opt/voptrhex0v
m-sequence_gen/sim/work/@_opt/voptrjbtgv
m-sequence_gen/sim/work/@_opt/voptsk7e1j
m-sequence_gen/sim/work/@_opt/voptvz0k2v
m-sequence_gen/sim/work/@_opt/voptw14t0v
m-sequence_gen/sim/work/@_opt/voptwhi7vw
m-sequence_gen/sim/work/@_opt/voptz7vnet
m-sequence_gen/sim/work/@_opt/_deps
m-sequence_gen/sim/work/@_opt1/vopt15krz1
m-sequence_gen/sim/work/@_opt1/vopt25vxj0
m-sequence_gen/sim/work/@_opt1/vopt2avv20
m-sequence_gen/sim/work/@_opt1/vopt52bmg1
m-sequence_gen/sim/work/@_opt1/vopt5mhqsz
m-sequence_gen/sim/work/@_opt1/vopt68ft21
m-sequence_gen/sim/work/@_opt1/vopt8fyfq1
m-sequence_gen/sim/work/@_opt1/vopt92vkt3
m-sequence_gen/sim/work/@_opt1/vopt990ij1
m-sequence_gen/sim/work/@_opt1/vopt9f4q51
m-sequence_gen/sim/work/@_opt1/voptcbned1
m-sequence_gen/sim/work/@_opt1/voptczjcq1
m-sequence_gen/sim/work/@_opt1/voptd9rkq1
m-sequence_gen/sim/work/@_opt1/voptff98q1
m-sequence_gen/sim/work/@_opt1/voptgjhezz
m-sequence_gen/sim/work/@_opt1/voptgvbbd1
m-sequence_gen/sim/work/@_opt1/voptgwggn0
m-sequence_gen/sim/work/@_opt1/voptjny5t1
m-sequence_gen/sim/work/@_opt1/voptjzx8h2
m-sequence_gen/sim/work/@_opt1/voptk37azz
m-sequence_gen/sim/work/@_opt1/voptky6dg0
m-sequence_gen/sim/work/@_opt1/voptqam2e1
m-sequence_gen/sim/work/@_opt1/voptqfj5h2
m-sequence_gen/sim/work/@_opt1/voptqjw7zz
m-sequence_gen/sim/work/@_opt1/voptrewag0
m-sequence_gen/sim/work/@_opt1/voptttazd1
m-sequence_gen/sim/work/@_opt1/voptvth420
m-sequence_gen/sim/work/@_opt1/voptvz81h2
m-sequence_gen/sim/work/@_opt1/voptyi1yf1
m-sequence_gen/sim/work/@_opt1/voptyxyvw1
m-sequence_gen/sim/work/@_opt1/voptzx51h0
m-sequence_gen/sim/work/@_opt1/_deps
m-sequence_gen/sim/work/control/_primary.dat
m-sequence_gen/sim/work/control/_primary.dbs
m-sequence_gen/sim/work/control/_primary.vhd
m-sequence_gen/sim/work/lfsr/_primary.dat
m-sequence_gen/sim/work/lfsr/_primary.dbs
m-sequence_gen/sim/work/lfsr/_primary.vhd
m-sequence_gen/sim/work/rom/_primary.dat
m-sequence_gen/sim/work/rom/_primary.dbs
m-sequence_gen/sim/work/rom/_primary.vhd
m-sequence_gen/sim/work/spi_master_tb/_primary.dat
m-sequence_gen/sim/work/spi_master_tb/_primary.dbs
m-sequence_gen/sim/work/spi_master_tb/_primary.vhd
m-sequence_gen/sim/work/sr/_primary.dat
m-sequence_gen/sim/work/sr/_primary.dbs
m-sequence_gen/sim/work/sr/_primary.vhd
m-sequence_gen/sim/work/testbench/_primary.dat
m-sequence_gen/sim/work/testbench/_primary.dbs
m-sequence_gen/sim/work/testbench/_primary.vhd
m-sequence_gen/sim/work/_info
m-sequence_gen/sim/work/_vmake
m-sequence_gen/testbench/tb.v
m-sequence_gen/仿真说明.txt
m-sequence_gen/sim/work/@_opt
m-sequence_gen/sim/work/@_opt1
m-sequence_gen/sim/work/control
m-sequence_gen/sim/work/lfsr
m-sequence_gen/sim/work/rom
m-sequence_gen/sim/work/spi_master_tb
m-sequence_gen/sim/work/sr
m-sequence_gen/sim/work/testbench
m-sequence_gen/sim/work/_temp
m-sequence_gen/sim/work
m-sequence_gen/rtl
m-sequence_gen/sim
m-sequence_gen/testbench
m-sequence_gen
m-sequence_gen/rtl/lfsr.v
m-sequence_gen/rtl/rom.v
m-sequence_gen/rtl/sr.v
m-sequence_gen/sim/sim.tcl
m-sequence_gen/sim/transcript
m-sequence_gen/sim/vsim.wlf
m-sequence_gen/sim/work/@_opt/vopt229biv
m-sequence_gen/sim/work/@_opt/vopt2sctj2
m-sequence_gen/sim/work/@_opt/vopt3rgjet
m-sequence_gen/sim/work/@_opt/vopt4r64gj
m-sequence_gen/sim/work/@_opt/vopt592nj2
m-sequence_gen/sim/work/@_opt/vopt6iy8iv
m-sequence_gen/sim/work/@_opt/vopt786get
m-sequence_gen/sim/work/@_opt/vopt88w1gj
m-sequence_gen/sim/work/@_opt/vopt92k5iv
m-sequence_gen/sim/work/@_opt/vopt9sqjj2
m-sequence_gen/sim/work/@_opt/voptafvdht
m-sequence_gen/sim/work/@_opt/voptbrhxfj
m-sequence_gen/sim/work/@_opt/voptc9dgj2
m-sequence_gen/sim/work/@_opt/voptdhb1xt
m-sequence_gen/sim/work/@_opt/voptezg9ht
m-sequence_gen/sim/work/@_opt/voptfz6tij
m-sequence_gen/sim/work/@_opt/voptgr0yzt
m-sequence_gen/sim/work/@_opt/voptgs2dj2
m-sequence_gen/sim/work/@_opt/vopthf66ht
m-sequence_gen/sim/work/@_opt/voptk3nygv
m-sequence_gen/sim/work/@_opt/voptk8nvzt
m-sequence_gen/sim/work/@_opt/voptk8t9y1
m-sequence_gen/sim/work/@_opt/voptndihyi
m-sequence_gen/sim/work/@_opt/voptqrbrzt
m-sequence_gen/sim/work/@_opt/voptrhex0v
m-sequence_gen/sim/work/@_opt/voptrjbtgv
m-sequence_gen/sim/work/@_opt/voptsk7e1j
m-sequence_gen/sim/work/@_opt/voptvz0k2v
m-sequence_gen/sim/work/@_opt/voptw14t0v
m-sequence_gen/sim/work/@_opt/voptwhi7vw
m-sequence_gen/sim/work/@_opt/voptz7vnet
m-sequence_gen/sim/work/@_opt/_deps
m-sequence_gen/sim/work/@_opt1/vopt15krz1
m-sequence_gen/sim/work/@_opt1/vopt25vxj0
m-sequence_gen/sim/work/@_opt1/vopt2avv20
m-sequence_gen/sim/work/@_opt1/vopt52bmg1
m-sequence_gen/sim/work/@_opt1/vopt5mhqsz
m-sequence_gen/sim/work/@_opt1/vopt68ft21
m-sequence_gen/sim/work/@_opt1/vopt8fyfq1
m-sequence_gen/sim/work/@_opt1/vopt92vkt3
m-sequence_gen/sim/work/@_opt1/vopt990ij1
m-sequence_gen/sim/work/@_opt1/vopt9f4q51
m-sequence_gen/sim/work/@_opt1/voptcbned1
m-sequence_gen/sim/work/@_opt1/voptczjcq1
m-sequence_gen/sim/work/@_opt1/voptd9rkq1
m-sequence_gen/sim/work/@_opt1/voptff98q1
m-sequence_gen/sim/work/@_opt1/voptgjhezz
m-sequence_gen/sim/work/@_opt1/voptgvbbd1
m-sequence_gen/sim/work/@_opt1/voptgwggn0
m-sequence_gen/sim/work/@_opt1/voptjny5t1
m-sequence_gen/sim/work/@_opt1/voptjzx8h2
m-sequence_gen/sim/work/@_opt1/voptk37azz
m-sequence_gen/sim/work/@_opt1/voptky6dg0
m-sequence_gen/sim/work/@_opt1/voptqam2e1
m-sequence_gen/sim/work/@_opt1/voptqfj5h2
m-sequence_gen/sim/work/@_opt1/voptqjw7zz
m-sequence_gen/sim/work/@_opt1/voptrewag0
m-sequence_gen/sim/work/@_opt1/voptttazd1
m-sequence_gen/sim/work/@_opt1/voptvth420
m-sequence_gen/sim/work/@_opt1/voptvz81h2
m-sequence_gen/sim/work/@_opt1/voptyi1yf1
m-sequence_gen/sim/work/@_opt1/voptyxyvw1
m-sequence_gen/sim/work/@_opt1/voptzx51h0
m-sequence_gen/sim/work/@_opt1/_deps
m-sequence_gen/sim/work/control/_primary.dat
m-sequence_gen/sim/work/control/_primary.dbs
m-sequence_gen/sim/work/control/_primary.vhd
m-sequence_gen/sim/work/lfsr/_primary.dat
m-sequence_gen/sim/work/lfsr/_primary.dbs
m-sequence_gen/sim/work/lfsr/_primary.vhd
m-sequence_gen/sim/work/rom/_primary.dat
m-sequence_gen/sim/work/rom/_primary.dbs
m-sequence_gen/sim/work/rom/_primary.vhd
m-sequence_gen/sim/work/spi_master_tb/_primary.dat
m-sequence_gen/sim/work/spi_master_tb/_primary.dbs
m-sequence_gen/sim/work/spi_master_tb/_primary.vhd
m-sequence_gen/sim/work/sr/_primary.dat
m-sequence_gen/sim/work/sr/_primary.dbs
m-sequence_gen/sim/work/sr/_primary.vhd
m-sequence_gen/sim/work/testbench/_primary.dat
m-sequence_gen/sim/work/testbench/_primary.dbs
m-sequence_gen/sim/work/testbench/_primary.vhd
m-sequence_gen/sim/work/_info
m-sequence_gen/sim/work/_vmake
m-sequence_gen/testbench/tb.v
m-sequence_gen/仿真说明.txt
m-sequence_gen/sim/work/@_opt
m-sequence_gen/sim/work/@_opt1
m-sequence_gen/sim/work/control
m-sequence_gen/sim/work/lfsr
m-sequence_gen/sim/work/rom
m-sequence_gen/sim/work/spi_master_tb
m-sequence_gen/sim/work/sr
m-sequence_gen/sim/work/testbench
m-sequence_gen/sim/work/_temp
m-sequence_gen/sim/work
m-sequence_gen/rtl
m-sequence_gen/sim
m-sequence_gen/testbench
m-sequence_gen
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