VGA实验_v1.docx
file_vga/
file_vga/vga.v
file_vga/vga.xdc
lab_vga/
lab_vga/lab_vga.cache/
lab_vga/lab_vga.cache/wt/
lab_vga/lab_vga.cache/wt/synthesis.wdf
lab_vga/lab_vga.cache/wt/webtalk_pa.xml
lab_vga/lab_vga.runs/
lab_vga/lab_vga.runs/.jobs/
lab_vga/lab_vga.runs/.jobs/vrs_config_1.xml
lab_vga/lab_vga.runs/.jobs/vrs_config_2.xml
lab_vga/lab_vga.runs/.jobs/vrs_config_3.xml
lab_vga/lab_vga.runs/clk_wiz_0_synth_1/
lab_vga/lab_vga.runs/clk_wiz_0_synth_1/.Vivado Synthesis.queue.rst
lab_vga/lab_vga.runs/clk_wiz_0_synth_1/.Xil/
lab_vga/lab_vga.runs/clk_wiz_0_synth_1/.Xil/clk_wiz_0_propImpl.xdc
lab_vga/lab_vga.runs/clk_wiz_0_synth_1/.vivado.begin.rst
lab_vga/lab_vga.runs/clk_wiz_0_synth_1/.vivado.end.rst
lab_vga/lab_vga.runs/clk_wiz_0_synth_1/ISEWrap.js
lab_vga/lab_vga.runs/clk_wiz_0_synth_1/ISEWrap.sh
lab_vga/lab_vga.runs/clk_wiz_0_synth_1/clk_wiz_0.dcp
lab_vga/lab_vga.runs/clk_wiz_0_synth_1/clk_wiz_0.tcl
lab_vga/lab_vga.runs/clk_wiz_0_synth_1/clk_wiz_0.vds
lab_vga/lab_vga.runs/clk_wiz_0_synth_1/clk_wiz_0_utilization_synth.pb
lab_vga/lab_vga.runs/clk_wiz_0_synth_1/clk_wiz_0_utilization_synth.rpt
lab_vga/lab_vga.runs/clk_wiz_0_synth_1/dont_touch.xdc
lab_vga/lab_vga.runs/clk_wiz_0_synth_1/gen_run.xml
lab_vga/lab_vga.runs/clk_wiz_0_synth_1/htr.txt
lab_vga/lab_vga.runs/clk_wiz_0_synth_1/project.wdf
lab_vga/lab_vga.runs/clk_wiz_0_synth_1/rundef.js
lab_vga/lab_vga.runs/clk_wiz_0_synth_1/runme.bat
lab_vga/lab_vga.runs/clk_wiz_0_synth_1/runme.log
lab_vga/lab_vga.runs/clk_wiz_0_synth_1/runme.sh
lab_vga/lab_vga.runs/clk_wiz_0_synth_1/vivado.jou
lab_vga/lab_vga.runs/clk_wiz_0_synth_1/vivado.pb
lab_vga/lab_vga.runs/impl_1/
lab_vga/lab_vga.runs/impl_1/.Vivado Implementation.queue.rst
lab_vga/lab_vga.runs/impl_1/.Xil/
lab_vga/lab_vga.runs/impl_1/.init_design.begin.rst
lab_vga/lab_vga.runs/impl_1/.init_design.end.rst
lab_vga/lab_vga.runs/impl_1/.opt_design.begin.rst
lab_vga/lab_vga.runs/impl_1/.opt_design.end.rst
lab_vga/lab_vga.runs/impl_1/.place_design.begin.rst
lab_vga/lab_vga.runs/impl_1/.place_design.end.rst
lab_vga/lab_vga.runs/impl_1/.route_design.begin.rst
lab_vga/lab_vga.runs/impl_1/.route_design.end.rst
lab_vga/lab_vga.runs/impl_1/.vivado.begin.rst
lab_vga/lab_vga.runs/impl_1/.vivado.end.rst
lab_vga/lab_vga.runs/impl_1/.write_bitstream.begin.rst
lab_vga/lab_vga.runs/impl_1/.write_bitstream.end.rst
lab_vga/lab_vga.runs/impl_1/ISEWrap.js
lab_vga/lab_vga.runs/impl_1/ISEWrap.sh
lab_vga/lab_vga.runs/impl_1/gen_run.xml
lab_vga/lab_vga.runs/impl_1/htr.txt
lab_vga/lab_vga.runs/impl_1/init_design.pb
lab_vga/lab_vga.runs/impl_1/opt_design.pb
lab_vga/lab_vga.runs/impl_1/place_design.pb
lab_vga/lab_vga.runs/impl_1/project.wdf
lab_vga/lab_vga.runs/impl_1/route_design.pb
lab_vga/lab_vga.runs/impl_1/rundef.js
lab_vga/lab_vga.runs/impl_1/runme.bat
lab_vga/lab_vga.runs/impl_1/runme.log
lab_vga/lab_vga.runs/impl_1/runme.sh
lab_vga/lab_vga.runs/impl_1/usage_statistics_webtalk.html
lab_vga/lab_vga.runs/impl_1/usage_statistics_webtalk.xml
lab_vga/lab_vga.runs/impl_1/vga.bit
lab_vga/lab_vga.runs/impl_1/vga.tcl
lab_vga/lab_vga.runs/impl_1/vga.vdi
lab_vga/lab_vga.runs/impl_1/vga_clock_utilization_placed.rpt
lab_vga/lab_vga.runs/impl_1/vga_control_sets_placed.rpt
lab_vga/lab_vga.runs/impl_1/vga_drc_routed.pb
lab_vga/lab_vga.runs/impl_1/vga_drc_routed.rpt
lab_vga/lab_vga.runs/impl_1/vga_io_placed.rpt
lab_vga/lab_vga.runs/impl_1/vga_opt.dcp
lab_vga/lab_vga.runs/impl_1/vga_placed.dcp
lab_vga/lab_vga.runs/impl_1/vga_power_routed.rpt
lab_vga/lab_vga.runs/impl_1/vga_power_summary_routed.pb
lab_vga/lab_vga.runs/impl_1/vga_route_status.pb
lab_vga/lab_vga.runs/impl_1/vga_route_status.rpt
lab_vga/lab_vga.runs/impl_1/vga_routed.dcp
lab_vga/lab_vga.runs/impl_1/vga_timing_summary_routed.pb
lab_vga/lab_vga.runs/impl_1/vga_timing_summary_routed.rpt
lab_vga/lab_vga.runs/impl_1/vga_utilization_placed.pb
lab_vga/lab_vga.runs/impl_1/vga_utilization_placed.rpt
lab_vga/lab_vga.runs/impl_1/vivado.jou
lab_vga/lab_vga.runs/impl_1/vivado.pb
lab_vga/lab_vga.runs/impl_1/write_bitstream.pb
lab_vga/lab_vga.runs/synth_1/
lab_vga/lab_vga.runs/synth_1/.Vivado Synthesis.queue.rst
lab_vga/lab_vga.runs/synth_1/.Xil/
lab_vga/lab_vga.runs/synth_1/.vivado.begin.rst
lab_vga/lab_vga.runs/synth_1/.vivado.end.rst
lab_vga/lab_vga.runs/synth_1/ISEWrap.js
lab_vga/lab_vga.runs/synth_1/ISEWrap.sh
lab_vga/lab_vga.runs/synth_1/dont_buffer.xdc
lab_vga/lab_vga.runs/synth_1/gen_run.xml
lab_vga/lab_vga.runs/synth_1/htr.txt
lab_vga/lab_vga.runs/synth_1/rundef.js
lab_vga/lab_vga.runs/synth_1/runme.bat
lab_vga/lab_vga.runs/synth_1/runme.log
lab_vga/lab_vga.runs/synth_1/runme.sh
lab_vga/lab_vga.runs/synth_1/vga.dcp
lab_vga/lab_vga.runs/synth_1/vga.tcl
lab_vga/lab_vga.runs/synth_1/vga.vds
lab_vga/lab_vga.runs/synth_1/vga_utilization_synth.pb
lab_vga/lab_vga.runs/synth_1/vga_utilization_synth.rpt
lab_vga/lab_vga.runs/synth_1/vivado.jou
lab_vga/lab_vga.runs/synth_1/vivado.pb
lab_vga/lab_vga.srcs/
lab_vga/lab_vga.srcs/constrs_1/
lab_vga/lab_vga.srcs/constrs_1/imports/
lab_vga/lab_vga.srcs/constrs_1/imports/file_vga/
lab_vga/lab_vga.srcs/constrs_1/imports/file_vga/vga.xdc
lab_vga/lab_vga.srcs/sources_1/
lab_vga/lab_vga.sr