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文件名称:fp_prj

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    2016-04-08
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    201.14kb
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FPGA Verilog 分频程序。用于板子验证及检测功能测试非常方便 -FPGA Verilog program , use for the board analyst and test . very helpfull
(系统自动生成,下载前可以参看下载内容)

下载文件列表

fp_prj/
fp_prj/db/
fp_prj/db/fp_verilog.(0).cnf.cdb
fp_prj/db/fp_verilog.(0).cnf.hdb
fp_prj/db/fp_verilog.ae.hdb
fp_prj/db/fp_verilog.asm.qmsg
fp_prj/db/fp_verilog.asm.rdb
fp_prj/db/fp_verilog.asm_labs.ddb
fp_prj/db/fp_verilog.cbx.xml
fp_prj/db/fp_verilog.cmp.cdb
fp_prj/db/fp_verilog.cmp.hdb
fp_prj/db/fp_verilog.cmp.kpt
fp_prj/db/fp_verilog.cmp.logdb
fp_prj/db/fp_verilog.cmp.rdb
fp_prj/db/fp_verilog.cmp.tdb
fp_prj/db/fp_verilog.cmp0.ddb
fp_prj/db/fp_verilog.db_info
fp_prj/db/fp_verilog.eco.cdb
fp_prj/db/fp_verilog.eda.qmsg
fp_prj/db/fp_verilog.fit.qmsg
fp_prj/db/fp_verilog.hier_info
fp_prj/db/fp_verilog.hif
fp_prj/db/fp_verilog.lpc.html
fp_prj/db/fp_verilog.lpc.rdb
fp_prj/db/fp_verilog.lpc.txt
fp_prj/db/fp_verilog.map.cdb
fp_prj/db/fp_verilog.map.hdb
fp_prj/db/fp_verilog.map.logdb
fp_prj/db/fp_verilog.map.qmsg
fp_prj/db/fp_verilog.pre_map.cdb
fp_prj/db/fp_verilog.pre_map.hdb
fp_prj/db/fp_verilog.rpp.qmsg
fp_prj/db/fp_verilog.rtlv.hdb
fp_prj/db/fp_verilog.rtlv_sg.cdb
fp_prj/db/fp_verilog.rtlv_sg_swap.cdb
fp_prj/db/fp_verilog.sgate.rvd
fp_prj/db/fp_verilog.sgate_sm.rvd
fp_prj/db/fp_verilog.sgdiff.cdb
fp_prj/db/fp_verilog.sgdiff.hdb
fp_prj/db/fp_verilog.sld_design_entry.sci
fp_prj/db/fp_verilog.sld_design_entry_dsc.sci
fp_prj/db/fp_verilog.smart_action.txt
fp_prj/db/fp_verilog.syn_hier_info
fp_prj/db/fp_verilog.tan.qmsg
fp_prj/db/fp_verilog.tis_db_list.ddb
fp_prj/db/fp_verilog.tmw_info
fp_prj/db/logic_util_heursitic.dat
fp_prj/db/prev_cmp_fp_verilog.asm.qmsg
fp_prj/db/prev_cmp_fp_verilog.eda.qmsg
fp_prj/db/prev_cmp_fp_verilog.fit.qmsg
fp_prj/db/prev_cmp_fp_verilog.map.qmsg
fp_prj/db/prev_cmp_fp_verilog.qmsg
fp_prj/db/prev_cmp_fp_verilog.tan.qmsg
fp_prj/fp_verilog.asm.rpt
fp_prj/fp_verilog.cdf
fp_prj/fp_verilog.done
fp_prj/fp_verilog.dpf
fp_prj/fp_verilog.eda.rpt
fp_prj/fp_verilog.fit.rpt
fp_prj/fp_verilog.fit.summary
fp_prj/fp_verilog.flow.rpt
fp_prj/fp_verilog.map.rpt
fp_prj/fp_verilog.map.summary
fp_prj/fp_verilog.pin
fp_prj/fp_verilog.pof
fp_prj/fp_verilog.qpf
fp_prj/fp_verilog.qsf
fp_prj/fp_verilog.qws
fp_prj/fp_verilog.tan.rpt
fp_prj/fp_verilog.tan.summary
fp_prj/fp_verilog.v
fp_prj/fp_verilog_nativelink_simulation.rpt
fp_prj/incremental_db/
fp_prj/incremental_db/compiled_partitions/
fp_prj/incremental_db/compiled_partitions/fp_verilog.root_partition.map.kpt
fp_prj/incremental_db/README
fp_prj/simulation/
fp_prj/simulation/modelsim/
fp_prj/simulation/modelsim/fp_verilog.sft
fp_prj/simulation/modelsim/fp_verilog.vo
fp_prj/simulation/modelsim/fp_verilog.vt
fp_prj/simulation/modelsim/fp_verilog_modelsim.xrf
fp_prj/simulation/modelsim/fp_verilog_run_msim_rtl_verilog.do
fp_prj/simulation/modelsim/fp_verilog_v.sdo
fp_prj/simulation/modelsim/modelsim.ini
fp_prj/simulation/modelsim/msim_transcript
fp_prj/simulation/modelsim/rtl_work/
fp_prj/simulation/modelsim/rtl_work/fp_verilog/
fp_prj/simulation/modelsim/rtl_work/fp_verilog/verilog.prw
fp_prj/simulation/modelsim/rtl_work/fp_verilog/verilog.psm
fp_prj/simulation/modelsim/rtl_work/fp_verilog/_primary.dat
fp_prj/simulation/modelsim/rtl_work/fp_verilog/_primary.dbs
fp_prj/simulation/modelsim/rtl_work/fp_verilog/_primary.vhd
fp_prj/simulation/modelsim/rtl_work/fp_verilog_vlg_tst/
fp_prj/simulation/modelsim/rtl_work/fp_verilog_vlg_tst/verilog.prw
fp_prj/simulation/modelsim/rtl_work/fp_verilog_vlg_tst/verilog.psm
fp_prj/simulation/modelsim/rtl_work/fp_verilog_vlg_tst/_primary.dat
fp_prj/simulation/modelsim/rtl_work/fp_verilog_vlg_tst/_primary.dbs
fp_prj/simulation/modelsim/rtl_work/fp_verilog_vlg_tst/_primary.vhd
fp_prj/simulation/modelsim/rtl_work/_info
fp_prj/simulation/modelsim/rtl_work/_temp/
fp_prj/simulation/modelsim/rtl_work/_vmake
fp_prj/simulation/modelsim/vsim.wlf

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