文件名称:A
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此为用verilog hdl编写的FPGAproject 其中A5+工程为带vga显示 分辨率600*800@60HZ 带字母显示（直接将ASCII码输入到寄存器中 窗口大小可调整）；A1工程为软核处理器 可配合使用 实测功能强大-This is written in Verilog HDL FPGAproject the A5+ engineering with VGA display resolution 600*800@60HZ with letters display directly to the ASCII code input to the registers window size can be adjusted) A1 engineering for soft core processor can be with the use of powerful features measured
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下载文件列表
A5+/.qsys_edit/filters.xml
A5+/.qsys_edit/preferences.xml
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