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文件名称:ISE_lab5

  • 所属分类：
    VHDL-FPGA-Verilog
  • 标签属性：
    [HTML]
  • 上传时间：
    2016-05-01
  • 文件大小：
    289.15kb
  • 已下载：
    0次
  • 提 供 者：
    岳****
  • 相关连接：
    无
  • 下载说明：
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修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

七段数码管的VHDL源代码 适合本科生学习使用-Seven segments of the VHDL source code for undergraduate learning to use
(系统自动生成,下载前可以参看下载内容)

下载文件列表

ISE_lab5/clk7seg.gise
ISE_lab5/clk7seg.ise
ISE_lab5/clk7seg.ise.pre_11.1_migration
ISE_lab5/clk7seg.ntrc_log
ISE_lab5/clk7seg.restore
ISE_lab5/clk7seg.ucf
ISE_lab5/clk7seg.vhd
ISE_lab5/clk7seg.xise
ISE_lab5/clk7seg_ngdbuild.xrpt
ISE_lab5/clk7seg_prev_built.ngd
ISE_lab5/clk7seg_summary.html
ISE_lab5/clk7seg_top.bgn
ISE_lab5/clk7seg_top.bit
ISE_lab5/clk7seg_top.bld
ISE_lab5/clk7seg_top.cmd_log
ISE_lab5/clk7seg_top.drc
ISE_lab5/clk7seg_top.lfp
ISE_lab5/clk7seg_top.lso
ISE_lab5/clk7seg_top.ncd
ISE_lab5/clk7seg_top.ngc
ISE_lab5/clk7seg_top.ngd
ISE_lab5/clk7seg_top.ngr
ISE_lab5/clk7seg_top.pad
ISE_lab5/clk7seg_top.par
ISE_lab5/clk7seg_top.pcf
ISE_lab5/clk7seg_top.prj
ISE_lab5/clk7seg_top.ptwx
ISE_lab5/clk7seg_top.stx
ISE_lab5/clk7seg_top.syr
ISE_lab5/clk7seg_top.twr
ISE_lab5/clk7seg_top.twx
ISE_lab5/clk7seg_top.unroutes
ISE_lab5/clk7seg_top.ut
ISE_lab5/clk7seg_top.vhd
ISE_lab5/clk7seg_top.xpi
ISE_lab5/clk7seg_top.xst
ISE_lab5/clk7seg_top_guide.ncd
ISE_lab5/clk7seg_top_map.map
ISE_lab5/clk7seg_top_map.mrp
ISE_lab5/clk7seg_top_map.ncd
ISE_lab5/clk7seg_top_map.ngm
ISE_lab5/clk7seg_top_map.xrpt
ISE_lab5/clk7seg_top_ngdbuild.xrpt
ISE_lab5/clk7seg_top_pad.csv
ISE_lab5/clk7seg_top_pad.txt
ISE_lab5/clk7seg_top_par.xrpt
ISE_lab5/clk7seg_top_prev_built.ngd
ISE_lab5/clk7seg_top_summary.html
ISE_lab5/clk7seg_top_summary.xml
ISE_lab5/clk7seg_top_usage.xml
ISE_lab5/clk7seg_top_vhdl.prj
ISE_lab5/clk7seg_top_xst.xrpt
ISE_lab5/clk7seg_xdb/cst.xbcd
ISE_lab5/clk7seg_xdb/tmp/ise/version
ISE_lab5/clk7seg_xdb/tmp/ise/__OBJSTORE__/HierarchicalDesign/HDProject/HDProject
ISE_lab5/clk7seg_xdb/tmp/ise/__OBJSTORE__/HierarchicalDesign/HDProject/HDProject_StrTbl
ISE_lab5/clk7seg_xdb/tmp/ise/__OBJSTORE__/HierarchicalDesign/__stored_object_table__
ISE_lab5/clk7seg_xdb/tmp/ise/__OBJSTORE__/PnAutoRun/Scripts/RunOnce_tcl
ISE_lab5/clk7seg_xdb/tmp/ise/__OBJSTORE__/PnAutoRun/Scripts/RunOnce_tcl_StrTbl
ISE_lab5/clk7seg_xdb/tmp/ise/__OBJSTORE__/ProjectNavigator/dpm_project_main/dpm_project_main
ISE_lab5/clk7seg_xdb/tmp/ise/__OBJSTORE__/ProjectNavigator/dpm_project_main/dpm_project_main_StrTbl
ISE_lab5/clk7seg_xdb/tmp/ise/__OBJSTORE__/ProjectNavigatorGui/CViewSelector
ISE_lab5/clk7seg_xdb/tmp/ise/__OBJSTORE__/ProjectNavigatorGui/CViewSelector_StrTbl
ISE_lab5/clk7seg_xdb/tmp/ise/__OBJSTORE__/ProjectNavigatorGui/File-SynthesisOnly
ISE_lab5/clk7seg_xdb/tmp/ise/__OBJSTORE__/ProjectNavigatorGui/File-SynthesisOnly_StrTbl
ISE_lab5/clk7seg_xdb/tmp/ise/__OBJSTORE__/ProjectNavigatorGui/GuiProjectData
ISE_lab5/clk7seg_xdb/tmp/ise/__OBJSTORE__/ProjectNavigatorGui/GuiProjectData_StrTbl
ISE_lab5/clk7seg_xdb/tmp/ise/__OBJSTORE__/ProjectNavigatorGui/Library-SynthesisOnly
ISE_lab5/clk7seg_xdb/tmp/ise/__OBJSTORE__/ProjectNavigatorGui/Library-SynthesisOnly_StrTbl
ISE_lab5/clk7seg_xdb/tmp/ise/__OBJSTORE__/ProjectNavigatorGui/Process-SynthesisOnly-
ISE_lab5/clk7seg_xdb/tmp/ise/__OBJSTORE__/ProjectNavigatorGui/Process-SynthesisOnly-DESUT_VHDL_ARCHITECTURE
ISE_lab5/clk7seg_xdb/tmp/ise/__OBJSTORE__/ProjectNavigatorGui/Process-SynthesisOnly-DESUT_VHDL_ARCHITECTURE_StrTbl
ISE_lab5/clk7seg_xdb/tmp/ise/__OBJSTORE__/ProjectNavigatorGui/Process-SynthesisOnly-_StrTbl
ISE_lab5/clk7seg_xdb/tmp/ise/__OBJSTORE__/ProjectNavigatorGui/Source-SynthesisOnly-AutoCompile
ISE_lab5/clk7seg_xdb/tmp/ise/__OBJSTORE__/ProjectNavigatorGui/Source-SynthesisOnly-AutoCompile_StrTbl
ISE_lab5/clk7seg_xdb/tmp/ise/__OBJSTORE__/xreport/Gc_RvReportViewer-Current-Module
ISE_lab5/clk7seg_xdb/tmp/ise/__OBJSTORE__/xreport/Gc_RvReportViewer-Current-Module_StrTbl
ISE_lab5/clk7seg_xdb/tmp/ise/__OBJSTORE__/xreport/Gc_RvReportViewer-Module-Data-clk7seg
ISE_lab5/clk7seg_xdb/tmp/ise/__OBJSTORE__/xreport/Gc_RvReportViewer-Module-Data-clk7seg_StrTbl
ISE_lab5/clk7seg_xdb/tmp/ise/__OBJSTORE__/xreport/Gc_RvReportViewer-Module-Data-clk7seg_top
ISE_lab5/clk7seg_xdb/tmp/ise/__OBJSTORE__/xreport/Gc_RvReportViewer-Module-Data-clk7seg_top_StrTbl
ISE_lab5/clk7seg_xdb/tmp/ise/__OBJSTORE__/xreport/Gc_RvReportViewer-Module-DataFactory-Default
ISE_lab5/clk7seg_xdb/tmp/ise/__OBJSTORE__/xreport/Gc_RvReportViewer-Module-DataFactory-Default_StrTbl
ISE_lab5/clk7seg_xdb/tmp/ise/__REGISTRY__/Autonym/regkeys
ISE_lab5/clk7seg_xdb/tmp/ise/__REGISTRY__/bitgen/regkeys
ISE_lab5/clk7seg_xdb/tmp/ise/__REGISTRY__/common/regkeys
ISE_lab5/clk7seg_xdb/tmp/ise/__REGISTRY__/ConstraintSystem/regkeys
ISE_lab5/clk7seg_xdb/tmp/ise/__REGISTRY__/cpldfit/regkeys
ISE_lab5/clk7seg_xdb/tmp/ise/__REGISTRY__/Cs/regkeys
ISE_lab5/clk7seg_xdb/tmp/ise/__REGISTRY__/dumpngdio/regkeys
ISE_lab5/clk7seg_xdb/tmp/ise/__REGISTRY__/fuse/regkeys
ISE_lab5/clk7seg_xdb/tmp/ise/__REGISTRY__/HierarchicalDesign/HDProject/regkeys
ISE_lab5/clk7seg_xdb/tmp/ise/__REGISTRY__/HierarchicalDesign/regkeys
ISE_lab5/clk7seg_xdb/tmp/ise/__REGISTRY__/hprep6/regkeys
ISE_lab5/clk7seg_xdb/tmp/ise/__REGISTRY__/idem/regkeys
ISE_lab5/clk7seg_xdb/tmp/ise/__REGISTRY__/map/regkeys
ISE_lab5/clk7seg_xdb/tmp/ise/__REGISTRY__/netgen/regkeys
ISE_lab5/clk7seg_xdb/tmp/ise/__REGISTRY__/ngc2edif/regkeys
ISE_lab5/clk7seg_xdb/tmp/ise/__REGISTRY__/ngcbuild/regkeys
ISE_lab5/clk7seg_xdb/tmp/ise/__REGISTRY__/ngdbuild/regkeys
ISE_lab5/clk7seg_x

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