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文件名称:ethernet

  • 所属分类：
    VHDL-FPGA-Verilog
  • 标签属性：
    [PDF]
  • 上传时间：
    2016-05-03
  • 文件大小：
    993.78kb
  • 已下载：
    0次
  • 提 供 者：
    T****
  • 相关连接：
    无
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修正介绍说明

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opencore上实现以太网mac层的开发版Verilog代码，含英文设计文档与datasheet。可在Modelsim中编译与仿真。-Achieve opencore Ethernet mac layer development version of Verilog code, design documents containing English and datasheet. Can be compiled with the simulation in Modelsim.
(系统自动生成,下载前可以参看下载内容)

下载文件列表

ethernet/
ethernet/CVS/
ethernet/CVS/Entries
ethernet/CVS/Entries.Log
ethernet/CVS/Repository
ethernet/CVS/Root
ethernet/CVS/Template
ethernet/README.txt
ethernet/bench/
ethernet/bench/CVS/
ethernet/bench/CVS/Entries
ethernet/bench/CVS/Entries.Log
ethernet/bench/CVS/Repository
ethernet/bench/CVS/Root
ethernet/bench/CVS/Template
ethernet/bench/verilog/
ethernet/bench/verilog/CVS/
ethernet/bench/verilog/CVS/Entries
ethernet/bench/verilog/CVS/Repository
ethernet/bench/verilog/CVS/Root
ethernet/bench/verilog/CVS/Template
ethernet/bench/verilog/eth_host.v
ethernet/bench/verilog/eth_memory.v
ethernet/bench/verilog/eth_phy.v
ethernet/bench/verilog/eth_phy_defines.v
ethernet/bench/verilog/tb_cop.v
ethernet/bench/verilog/tb_eth_defines.v
ethernet/bench/verilog/tb_eth_top.v
ethernet/bench/verilog/tb_ethernet.v
ethernet/bench/verilog/tb_ethernet_with_cop.v
ethernet/bench/verilog/wb_bus_mon.v
ethernet/bench/verilog/wb_master32.v
ethernet/bench/verilog/wb_master_behavioral.v
ethernet/bench/verilog/wb_model_defines.v
ethernet/bench/verilog/wb_slave_behavioral.v
ethernet/doc/
ethernet/doc/CVS/
ethernet/doc/CVS/Entries
ethernet/doc/CVS/Entries.Log
ethernet/doc/CVS/Repository
ethernet/doc/CVS/Root
ethernet/doc/CVS/Template
ethernet/doc/eth_design_document.pdf
ethernet/doc/eth_speci.pdf
ethernet/doc/ethernet_datasheet_OC_head.pdf
ethernet/doc/ethernet_product_brief_OC_head.pdf
ethernet/doc/src/
ethernet/doc/src/CVS/
ethernet/doc/src/CVS/Entries
ethernet/doc/src/CVS/Repository
ethernet/doc/src/CVS/Root
ethernet/doc/src/CVS/Template
ethernet/doc/src/eth_design_document.doc
ethernet/doc/src/eth_speci.doc
ethernet/doc/src/ethernet_datasheet_OC_head.doc
ethernet/doc/src/ethernet_product_brief_OC_head.doc
ethernet/rtl/
ethernet/rtl/CVS/
ethernet/rtl/CVS/Entries
ethernet/rtl/CVS/Entries.Log
ethernet/rtl/CVS/Repository
ethernet/rtl/CVS/Root
ethernet/rtl/CVS/Template
ethernet/rtl/verilog/
ethernet/rtl/verilog/BUGS
ethernet/rtl/verilog/CVS/
ethernet/rtl/verilog/CVS/Entries
ethernet/rtl/verilog/CVS/Repository
ethernet/rtl/verilog/CVS/Root
ethernet/rtl/verilog/CVS/Template
ethernet/rtl/verilog/TODO
ethernet/rtl/verilog/eth_clockgen.v
ethernet/rtl/verilog/eth_cop.v
ethernet/rtl/verilog/eth_crc.v
ethernet/rtl/verilog/eth_defines.v
ethernet/rtl/verilog/eth_fifo.v
ethernet/rtl/verilog/eth_maccontrol.v
ethernet/rtl/verilog/eth_macstatus.v
ethernet/rtl/verilog/eth_miim.v
ethernet/rtl/verilog/eth_outputcontrol.v
ethernet/rtl/verilog/eth_random.v
ethernet/rtl/verilog/eth_receivecontrol.v
ethernet/rtl/verilog/eth_register.v
ethernet/rtl/verilog/eth_registers.v
ethernet/rtl/verilog/eth_rxaddrcheck.v
ethernet/rtl/verilog/eth_rxcounters.v
ethernet/rtl/verilog/eth_rxethmac.v
ethernet/rtl/verilog/eth_rxstatem.v
ethernet/rtl/verilog/eth_shiftreg.v
ethernet/rtl/verilog/eth_spram_256x32.v
ethernet/rtl/verilog/eth_top.v
ethernet/rtl/verilog/eth_transmitcontrol.v
ethernet/rtl/verilog/eth_txcounters.v
ethernet/rtl/verilog/eth_txethmac.v
ethernet/rtl/verilog/eth_txstatem.v
ethernet/rtl/verilog/eth_wishbone.v
ethernet/rtl/verilog/timescale.v
ethernet/rtl/verilog/xilinx_dist_ram_16x32.v
ethernet/sim/
ethernet/sim/CVS/
ethernet/sim/CVS/Entries
ethernet/sim/CVS/Entries.Log
ethernet/sim/CVS/Repository
ethernet/sim/CVS/Root
ethernet/sim/CVS/Template
ethernet/sim/rtl_sim/
ethernet/sim/rtl_sim/CVS/
ethernet/sim/rtl_sim/CVS/Entries
ethernet/sim/rtl_sim/CVS/Entries.Log
ethernet/sim/rtl_sim/CVS/Repository
ethernet/sim/rtl_sim/CVS/Root
ethernet/sim/rtl_sim/CVS/Template
ethernet/sim/rtl_sim/bin/
ethernet/sim/rtl_sim/bin/CVS/
ethernet/sim/rtl_sim/bin/CVS/Entries
ethernet/sim/rtl_sim/bin/CVS/Entries.Log
ethernet/sim/rtl_sim/bin/CVS/Repository
ethernet/sim/rtl_sim/bin/CVS/Root
ethernet/sim/rtl_sim/bin/CVS/Template
ethernet/sim/rtl_sim/bin/INCA_libs/
ethernet/sim/rtl_sim/bin/INCA_libs/CVS/
ethernet/sim/rtl_sim/bin/INCA_libs/CVS/Entries
ethernet/sim/rtl_sim/bin/INCA_libs/CVS/Entries.Log
ethernet/sim/rtl_sim/bin/INCA_libs/CVS/Repository
ethernet/sim/rtl_sim/bin/INCA_libs/CVS/Root
ethernet/sim/rtl_sim/bin/INCA_libs/CVS/Template
ethernet/sim/rtl_sim/bin/INCA_libs/worklib/
ethernet/sim/rtl_sim/bin/INCA_libs/worklib/CVS/
ethernet/sim/rtl_sim/bin/INCA_libs/worklib/CVS/Entries
ethernet/sim/rtl_sim/bin/INCA_libs/worklib/CVS/Repository
ethernet/sim/rtl_sim/bin/INCA_libs/worklib/CVS/Root
ethernet/sim/rtl_sim/bin/INCA_libs/worklib/CVS/Template
ethernet/sim/rtl_sim/bin/INCA_libs/worklib/dir_keeper
ethernet/sim/rtl_sim/bin/artisan_file_list.lst
ethernet/sim/rtl_sim/bin/cds.lib
ethernet/sim/rtl_sim/bin/hdl.var
ethernet/sim/rtl_sim/bin/ncelab.args
ethernet/sim/rtl_sim/bin/ncelab_xilinx.args
ethernet/sim/rtl_sim/bin/ncsim.rc
ethernet/sim/rtl_sim/bin/ncsim_waves.rc
ethernet/sim/rtl_sim/bin/rtl_file_list.lst
ethernet/sim/rtl_sim/bin/run_sim
ethernet/sim/rtl_sim/bin/sim_file_list.lst
ethernet/sim/rtl_sim/bin/xilinx_file_list.lst
ethernet/sim/rtl_sim/log/
ethernet/sim/rtl_sim/log/CVS/
ethernet/sim/rtl_sim/log/CVS/Entries
ethernet/sim/rtl_sim/log/CVS/Repository
ethernet/sim/rtl_sim/log/CVS/Root
ethernet/sim/rtl_sim/log/CVS/Template
ethernet/sim/rtl_sim/log/dir_keeper
ethernet/sim/rtl_sim/modelsim_sim/
ethernet/si

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