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文件名称:LBG64_double_CLK

  • 所属分类：
    VHDL-FPGA-Verilog
  • 标签属性：
    [ASM] [源码]
  • 上传时间：
    2016-05-10
  • 文件大小：
    577.59kb
  • 已下载：
    0次
  • 提 供 者：
    崔***
  • 相关连接：
    无
  • 下载说明：
    别用迅雷下载，失败请重下，重下不扣分！
修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

数据压缩算法的硬件实现ASIC&FPGA（矢量量化算法）-Data compression algorithm implemented in hardware ASIC &　FPGA (vector quantization algorithm)
(系统自动生成,下载前可以参看下载内容)

下载文件列表

LBG64_double_CLK/
LBG64_double_CLK/LBG.v
LBG64_double_CLK/LBG.v.bak
LBG64_double_CLK/LBG_64.cr.mti
LBG64_double_CLK/LBG_64.mpf
LBG64_double_CLK/LBG_tb.v
LBG64_double_CLK/LBG_tb.v.bak
LBG64_double_CLK/cal_disteu.v
LBG64_double_CLK/cal_disteu.v.bak
LBG64_double_CLK/clk_div.v
LBG64_double_CLK/codebook_div.v
LBG64_double_CLK/codebook_div.v.bak
LBG64_double_CLK/codebook_init.v
LBG64_double_CLK/codebook_init.v.bak
LBG64_double_CLK/codebook_top.v
LBG64_double_CLK/codebook_top.v.bak
LBG64_double_CLK/codebook_update.v
LBG64_double_CLK/codebook_update.v.bak
LBG64_double_CLK/divider.v
LBG64_double_CLK/divider.v.bak
LBG64_double_CLK/mult.v
LBG64_double_CLK/mult0.v
LBG64_double_CLK/mult0.v.bak
LBG64_double_CLK/mult2.v
LBG64_double_CLK/mult2.v.bak
LBG64_double_CLK/test_data.dat
LBG64_double_CLK/transcript
LBG64_double_CLK/vector_g.v
LBG64_double_CLK/vector_g.v.bak
LBG64_double_CLK/vsim.wlf
LBG64_double_CLK/weight.v
LBG64_double_CLK/work/
LBG64_double_CLK/work/@l@b@g/
LBG64_double_CLK/work/@l@b@g/_primary.dat
LBG64_double_CLK/work/@l@b@g/_primary.dbs
LBG64_double_CLK/work/@l@b@g/_primary.vhd
LBG64_double_CLK/work/@l@b@g/verilog.asm
LBG64_double_CLK/work/@l@b@g/verilog.rw
LBG64_double_CLK/work/_info
LBG64_double_CLK/work/_temp/
LBG64_double_CLK/work/_temp/vlog0f4bq9
LBG64_double_CLK/work/_temp/vlog0qh00v
LBG64_double_CLK/work/_temp/vlog1zv4q8
LBG64_double_CLK/work/_temp/vlog29qyze
LBG64_double_CLK/work/_temp/vlog3eg90j
LBG64_double_CLK/work/_temp/vlog4ym9x6
LBG64_double_CLK/work/_temp/vlog5iv8h4
LBG64_double_CLK/work/_temp/vlog79dz4c
LBG64_double_CLK/work/_temp/vlog7iyf87
LBG64_double_CLK/work/_temp/vlog9d12nz
LBG64_double_CLK/work/_temp/vlogb5jt7r
LBG64_double_CLK/work/_temp/vlogcd5xxf
LBG64_double_CLK/work/_temp/vlogebe5j0
LBG64_double_CLK/work/_temp/vloggr1e5y
LBG64_double_CLK/work/_temp/vlogixg7rk
LBG64_double_CLK/work/_temp/vlogjnvj11
LBG64_double_CLK/work/_temp/vlognan7i0
LBG64_double_CLK/work/_temp/vlogsf4vje
LBG64_double_CLK/work/_temp/vlogsjf52n
LBG64_double_CLK/work/_temp/vlogt1e73f
LBG64_double_CLK/work/_temp/vlogx1z1v7
LBG64_double_CLK/work/_temp/vlogy5ifeq
LBG64_double_CLK/work/_temp/vlogz1rstm
LBG64_double_CLK/work/_temp/vlogz2hd43
LBG64_double_CLK/work/_temp/vlogzdk2ej
LBG64_double_CLK/work/_vmake
LBG64_double_CLK/work/cal_disteu/
LBG64_double_CLK/work/cal_disteu/_primary.dat
LBG64_double_CLK/work/cal_disteu/_primary.dbs
LBG64_double_CLK/work/cal_disteu/_primary.vhd
LBG64_double_CLK/work/cal_disteu/verilog.asm
LBG64_double_CLK/work/cal_disteu/verilog.rw
LBG64_double_CLK/work/clk_div/
LBG64_double_CLK/work/clk_div/_primary.dat
LBG64_double_CLK/work/clk_div/_primary.dbs
LBG64_double_CLK/work/clk_div/_primary.vhd
LBG64_double_CLK/work/clk_div/verilog.asm
LBG64_double_CLK/work/clk_div/verilog.rw
LBG64_double_CLK/work/codebook_div/
LBG64_double_CLK/work/codebook_div/_primary.dat
LBG64_double_CLK/work/codebook_div/_primary.dbs
LBG64_double_CLK/work/codebook_div/_primary.vhd
LBG64_double_CLK/work/codebook_div/verilog.asm
LBG64_double_CLK/work/codebook_div/verilog.rw
LBG64_double_CLK/work/codebook_init/
LBG64_double_CLK/work/codebook_init/_primary.dat
LBG64_double_CLK/work/codebook_init/_primary.dbs
LBG64_double_CLK/work/codebook_init/_primary.vhd
LBG64_double_CLK/work/codebook_init/verilog.asm
LBG64_double_CLK/work/codebook_init/verilog.rw
LBG64_double_CLK/work/codebook_top/
LBG64_double_CLK/work/codebook_top/_primary.dat
LBG64_double_CLK/work/codebook_top/_primary.dbs
LBG64_double_CLK/work/codebook_top/_primary.vhd
LBG64_double_CLK/work/codebook_top/verilog.asm
LBG64_double_CLK/work/codebook_top/verilog.rw
LBG64_double_CLK/work/codebook_update/
LBG64_double_CLK/work/codebook_update/_primary.dat
LBG64_double_CLK/work/codebook_update/_primary.dbs
LBG64_double_CLK/work/codebook_update/_primary.vhd
LBG64_double_CLK/work/codebook_update/verilog.asm
LBG64_double_CLK/work/codebook_update/verilog.rw
LBG64_double_CLK/work/divider/
LBG64_double_CLK/work/divider/_primary.dat
LBG64_double_CLK/work/divider/_primary.dbs
LBG64_double_CLK/work/divider/_primary.vhd
LBG64_double_CLK/work/divider/verilog.asm
LBG64_double_CLK/work/divider/verilog.rw
LBG64_double_CLK/work/mult0/
LBG64_double_CLK/work/mult0/_primary.dat
LBG64_double_CLK/work/mult0/_primary.dbs
LBG64_double_CLK/work/mult0/_primary.vhd
LBG64_double_CLK/work/mult0/verilog.asm
LBG64_double_CLK/work/mult0/verilog.rw
LBG64_double_CLK/work/mult1/
LBG64_double_CLK/work/mult1/_primary.dat
LBG64_double_CLK/work/mult1/_primary.dbs
LBG64_double_CLK/work/mult1/_primary.vhd
LBG64_double_CLK/work/mult1/verilog.asm
LBG64_double_CLK/work/mult1/verilog.rw
LBG64_double_CLK/work/mult2/
LBG64_double_CLK/work/mult2/_primary.dat
LBG64_double_CLK/work/mult2/_primary.dbs
LBG64_double_CLK/work/mult2/_primary.vhd
LBG64_double_CLK/work/mult2/verilog.asm
LBG64_double_CLK/work/mult2/verilog.rw
LBG64_double_CLK/work/tb_@l@b@g/
LBG64_double_CLK/work/tb_@l@b@g/_primary.dat
LBG64_double_CLK/work/tb_@l@b@g/_primary.dbs
LBG64_double_CLK/work/tb_@l@b@g/_primary.vhd
LBG64_double_CLK/work/tb_@l@b@g/verilog.asm
LBG64_double_CLK/work/tb_@l@b@g/verilog.rw
LBG64_double_CLK/work/vector_g/
LBG64_double_CLK/work/vector_g/_primary.d

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