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文件名称:shizhong

  • 所属分类：
    VHDL-FPGA-Verilog
  • 标签属性：
  • 上传时间：
    2016-05-27
  • 文件大小：
    362.44kb
  • 已下载：
    1次
  • 提 供 者：
    李****
  • 相关连接：
    无
  • 下载说明：
    别用迅雷下载，失败请重下，重下不扣分！
修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

这是用VHDL编写的数字逻辑时钟电路，实现计时和由23:59到00:00转换的功能，已经在FPGA中测试通过！-This is written in VHDL digital logic circuit。It can realize the function of timing and by 23:59 to 00:00 conversion, has been in the FPGA test through!
(系统自动生成,下载前可以参看下载内容)

下载文件列表

shizhong/
shizhong/db/
shizhong/db/prev_cmp_shuzishizhong.asm.qmsg
shizhong/db/prev_cmp_shuzishizhong.fit.qmsg
shizhong/db/prev_cmp_shuzishizhong.map.qmsg
shizhong/db/prev_cmp_shuzishizhong.qmsg
shizhong/db/prev_cmp_shuzishizhong.tan.qmsg
shizhong/db/shuzishizhong.(0).cnf.cdb
shizhong/db/shuzishizhong.(0).cnf.hdb
shizhong/db/shuzishizhong.asm.qmsg
shizhong/db/shuzishizhong.asm_labs.ddb
shizhong/db/shuzishizhong.cbx.xml
shizhong/db/shuzishizhong.cmp.bpm
shizhong/db/shuzishizhong.cmp.cdb
shizhong/db/shuzishizhong.cmp.ecobp
shizhong/db/shuzishizhong.cmp.hdb
shizhong/db/shuzishizhong.cmp.logdb
shizhong/db/shuzishizhong.cmp.rdb
shizhong/db/shuzishizhong.cmp.tdb
shizhong/db/shuzishizhong.cmp0.ddb
shizhong/db/shuzishizhong.cmp2.ddb
shizhong/db/shuzishizhong.cmp_bb.cdb
shizhong/db/shuzishizhong.cmp_bb.hdb
shizhong/db/shuzishizhong.cmp_bb.logdb
shizhong/db/shuzishizhong.cmp_bb.rcf
shizhong/db/shuzishizhong.db_info
shizhong/db/shuzishizhong.dbp
shizhong/db/shuzishizhong.eco.cdb
shizhong/db/shuzishizhong.fit.qmsg
shizhong/db/shuzishizhong.hier_info
shizhong/db/shuzishizhong.hif
shizhong/db/shuzishizhong.map.bpm
shizhong/db/shuzishizhong.map.cdb
shizhong/db/shuzishizhong.map.ecobp
shizhong/db/shuzishizhong.map.hdb
shizhong/db/shuzishizhong.map.logdb
shizhong/db/shuzishizhong.map.qmsg
shizhong/db/shuzishizhong.map_bb.cdb
shizhong/db/shuzishizhong.map_bb.hdb
shizhong/db/shuzishizhong.map_bb.logdb
shizhong/db/shuzishizhong.pre_map.cdb
shizhong/db/shuzishizhong.pre_map.hdb
shizhong/db/shuzishizhong.psp
shizhong/db/shuzishizhong.pss
shizhong/db/shuzishizhong.rtlv.hdb
shizhong/db/shuzishizhong.rtlv_sg.cdb
shizhong/db/shuzishizhong.rtlv_sg_swap.cdb
shizhong/db/shuzishizhong.sgdiff.cdb
shizhong/db/shuzishizhong.sgdiff.hdb
shizhong/db/shuzishizhong.signalprobe.cdb
shizhong/db/shuzishizhong.sld_design_entry.sci
shizhong/db/shuzishizhong.sld_design_entry_dsc.sci
shizhong/db/shuzishizhong.syn_hier_info
shizhong/db/shuzishizhong.tan.qmsg
shizhong/db/shuzishizhong.tis_db_list.ddb
shizhong/shuzishizhong.asm.rpt
shizhong/shuzishizhong.done
shizhong/shuzishizhong.dpf
shizhong/shuzishizhong.fit.rpt
shizhong/shuzishizhong.fit.smsg
shizhong/shuzishizhong.fit.summary
shizhong/shuzishizhong.flow.rpt
shizhong/shuzishizhong.map.rpt
shizhong/shuzishizhong.map.summary
shizhong/shuzishizhong.pin
shizhong/shuzishizhong.pof
shizhong/shuzishizhong.qpf
shizhong/shuzishizhong.qsf
shizhong/shuzishizhong.qws
shizhong/shuzishizhong.sof
shizhong/shuzishizhong.tan.rpt
shizhong/shuzishizhong.tan.summary
shizhong/shuzishizhong.vhd

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