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文件名称:FPGA_Project

  • 所属分类：
    source in ebook
  • 标签属性：
    [HTML]
  • 上传时间：
    2016-06-03
  • 文件大小：
    3.93mb
  • 已下载：
    0次
  • 提 供 者：
    小***
  • 相关连接：
    无
  • 下载说明：
    别用迅雷下载，失败请重下，重下不扣分！
修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

USB 2.0的数据传输verilog程序，采用的是slave状态机实现其功能。其中包括读、写功能

-USB 2.0 data transfer verilog program, using the slave state machine functionality. Including reading and writing functions
(系统自动生成,下载前可以参看下载内容)

下载文件列表

FPGA_Project/db/altsyncram_0q14.tdf
FPGA_Project/db/cmpr_5cc.tdf
FPGA_Project/db/cmpr_6cc.tdf
FPGA_Project/db/cmpr_8cc.tdf
FPGA_Project/db/cmpr_9cc.tdf
FPGA_Project/db/cntr_02j.tdf
FPGA_Project/db/cntr_0ci.tdf
FPGA_Project/db/cntr_7ai.tdf
FPGA_Project/db/cntr_gui.tdf
FPGA_Project/db/cntr_sbi.tdf
FPGA_Project/db/decode_rqf.tdf
FPGA_Project/db/fpga_master.(0).cnf.cdb
FPGA_Project/db/fpga_master.(0).cnf.hdb
FPGA_Project/db/fpga_master.(1).cnf.cdb
FPGA_Project/db/fpga_master.(1).cnf.hdb
FPGA_Project/db/fpga_master.(2).cnf.cdb
FPGA_Project/db/fpga_master.(2).cnf.hdb
FPGA_Project/db/fpga_master.(3).cnf.cdb
FPGA_Project/db/fpga_master.(3).cnf.hdb
FPGA_Project/db/fpga_master.(4).cnf.cdb
FPGA_Project/db/fpga_master.(4).cnf.hdb
FPGA_Project/db/fpga_master.(5).cnf.cdb
FPGA_Project/db/fpga_master.(5).cnf.hdb
FPGA_Project/db/fpga_master.(6).cnf.cdb
FPGA_Project/db/fpga_master.(6).cnf.hdb
FPGA_Project/db/fpga_master.(7).cnf.cdb
FPGA_Project/db/fpga_master.(7).cnf.hdb
FPGA_Project/db/fpga_master.(8).cnf.cdb
FPGA_Project/db/fpga_master.(8).cnf.hdb
FPGA_Project/db/fpga_master.amm.cdb
FPGA_Project/db/fpga_master.asm.qmsg
FPGA_Project/db/fpga_master.asm.rdb
FPGA_Project/db/fpga_master.asm_labs.ddb
FPGA_Project/db/fpga_master.cbx.xml
FPGA_Project/db/fpga_master.cmp.bpm
FPGA_Project/db/fpga_master.cmp.cdb
FPGA_Project/db/fpga_master.cmp.hdb
FPGA_Project/db/fpga_master.cmp.kpt
FPGA_Project/db/fpga_master.cmp.logdb
FPGA_Project/db/fpga_master.cmp.rdb
FPGA_Project/db/fpga_master.cmp_merge.kpt
FPGA_Project/db/fpga_master.cycloneive_io_sim_cache.45um_ff_1200mv_0c_fast.hsd
FPGA_Project/db/fpga_master.cycloneive_io_sim_cache.45um_ss_1200mv_0c_slow.hsd
FPGA_Project/db/fpga_master.cycloneive_io_sim_cache.45um_ss_1200mv_85c_slow.hsd
FPGA_Project/db/fpga_master.db_info
FPGA_Project/db/fpga_master.eda.qmsg
FPGA_Project/db/fpga_master.fit.qmsg
FPGA_Project/db/fpga_master.hier_info
FPGA_Project/db/fpga_master.hif
FPGA_Project/db/fpga_master.idb.cdb
FPGA_Project/db/fpga_master.lpc.html
FPGA_Project/db/fpga_master.lpc.rdb
FPGA_Project/db/fpga_master.lpc.txt
FPGA_Project/db/fpga_master.map.bpm
FPGA_Project/db/fpga_master.map.cdb
FPGA_Project/db/fpga_master.map.hdb
FPGA_Project/db/fpga_master.map.kpt
FPGA_Project/db/fpga_master.map.logdb
FPGA_Project/db/fpga_master.map.qmsg
FPGA_Project/db/fpga_master.map_bb.cdb
FPGA_Project/db/fpga_master.map_bb.hdb
FPGA_Project/db/fpga_master.map_bb.logdb
FPGA_Project/db/fpga_master.pre_map.cdb
FPGA_Project/db/fpga_master.pre_map.hdb
FPGA_Project/db/fpga_master.rtlv.hdb
FPGA_Project/db/fpga_master.rtlv_sg.cdb
FPGA_Project/db/fpga_master.rtlv_sg_swap.cdb
FPGA_Project/db/fpga_master.sgdiff.cdb
FPGA_Project/db/fpga_master.sgdiff.hdb
FPGA_Project/db/fpga_master.sld_design_entry.sci
FPGA_Project/db/fpga_master.sld_design_entry_dsc.sci
FPGA_Project/db/fpga_master.smart_action.txt
FPGA_Project/db/fpga_master.sta.qmsg
FPGA_Project/db/fpga_master.sta.rdb
FPGA_Project/db/fpga_master.sta_cmp.8_slow_1200mv_85c.tdb
FPGA_Project/db/fpga_master.syn_hier_info
FPGA_Project/db/fpga_master.tiscmp.fastest_slow_1200mv_0c.ddb
FPGA_Project/db/fpga_master.tiscmp.fastest_slow_1200mv_85c.ddb
FPGA_Project/db/fpga_master.tiscmp.fast_1200mv_0c.ddb
FPGA_Project/db/fpga_master.tiscmp.slow_1200mv_0c.ddb
FPGA_Project/db/fpga_master.tiscmp.slow_1200mv_85c.ddb
FPGA_Project/db/fpga_master.tis_db_list.ddb
FPGA_Project/db/logic_util_heursitic.dat
FPGA_Project/db/mux_aoc.tdf
FPGA_Project/db/prev_cmp_fpga_master.qmsg
FPGA_Project/fpga_master.asm.rpt
FPGA_Project/fpga_master.bdf
FPGA_Project/fpga_master.bsf
FPGA_Project/fpga_master.cdf
FPGA_Project/fpga_master.done
FPGA_Project/fpga_master.eda.rpt
FPGA_Project/fpga_master.fit.rpt
FPGA_Project/fpga_master.fit.smsg
FPGA_Project/fpga_master.fit.summary
FPGA_Project/fpga_master.flow.rpt
FPGA_Project/fpga_master.jdi
FPGA_Project/fpga_master.map.rpt
FPGA_Project/fpga_master.map.summary
FPGA_Project/fpga_master.merge.rpt
FPGA_Project/fpga_master.pin
FPGA_Project/fpga_master.pof
FPGA_Project/fpga_master.qpf
FPGA_Project/fpga_master.qsf
FPGA_Project/fpga_master.qsf.bak
FPGA_Project/fpga_master.sof
FPGA_Project/fpga_master.sta.rpt
FPGA_Project/fpga_master.sta.summary
FPGA_Project/fpga_master.vhd
FPGA_Project/fpga_master.vhd.bak
FPGA_Project/fpga_master_assignment_defaults.qdf
FPGA_Project/fpga_master_sync.bdf
FPGA_Project/greybox_tmp/cbx_args.txt
FPGA_Project/incremental_db/compiled_partitions/fpga_master.autoh_e4eb1.map.cdb
FPGA_Project/incremental_db/compiled_partitions/fpga_master.autoh_e4eb1.map.dpi
FPGA_Project/incremental_db/compiled_partitions/fpga_master.autoh_e4eb1.map.hdb
FPGA_Project/incremental_db/compiled_partitions/fpga_master.autoh_e4eb1.map.kpt
FPGA_Project/incremental_db/compiled_partitions/fpga_master.autoh_e4eb1.map.logdb
FPGA_Project/incremental_db/compiled_partitions/fpga_master.autol_7d8f1.map.cdb
FPGA_Project/incremental_db/compiled_partitions/fpga_master.autol_7d8f1.map.dpi
FPGA_Project/incremental_db/compiled_partitions/fpga_master.autol_7d8f1.map.hdb
FPGA_Project/incremental_db/compiled_partitions/fpga_master.autol_7d8f1.map.kpt
FPGA_Project/incremental_db/compiled_partitions/fpga_master.autol_7d8f1.ma

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