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文件名称:PingPang_buffer_20160526

  • 所属分类：
    VHDL-FPGA-Verilog
  • 标签属性：
    [Linux] [SHELL] [源码]
  • 上传时间：
    2016-06-03
  • 文件大小：
    2.31mb
  • 已下载：
    1次
  • 提 供 者：
    贾****
  • 相关连接：
    无
  • 下载说明：
    别用迅雷下载，失败请重下，重下不扣分！
修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

源码仿真 乒乓 缓存，实现数据流的传输，含有仿真测试文件，vivado工程。-Source simulation　ping-pong　cache data stream transmission, the file containing the simulation test, vivado project.
(系统自动生成,下载前可以参看下载内容)

下载文件列表

PingPang_buffer_20160526/test.cache/wt/synthesis.wdf
PingPang_buffer_20160526/test.cache/wt/webtalk_pa.xml
PingPang_buffer_20160526/test.cache/wt/xsim.wdf
PingPang_buffer_20160526/test.runs/.jobs/vrs_config_1.xml
PingPang_buffer_20160526/test.runs/.jobs/vrs_config_2.xml
PingPang_buffer_20160526/test.runs/.jobs/vrs_config_3.xml
PingPang_buffer_20160526/test.runs/.jobs/vrs_config_4.xml
PingPang_buffer_20160526/test.runs/.jobs/vrs_config_5.xml
PingPang_buffer_20160526/test.runs/.jobs/vrs_config_6.xml
PingPang_buffer_20160526/test.runs/.jobs/vrs_config_7.xml
PingPang_buffer_20160526/test.runs/.jobs/vrs_config_8.xml
PingPang_buffer_20160526/test.runs/blk_mem_gen_0_synth_1/vivado.pb
PingPang_buffer_20160526/test.runs/srio_gen2_0_synth_1/vivado.pb
PingPang_buffer_20160526/test.sim/sim_1/behav/blk_mem_gen_0.mif
PingPang_buffer_20160526/test.sim/sim_1/behav/compile.bat
PingPang_buffer_20160526/test.sim/sim_1/behav/compile.sh
PingPang_buffer_20160526/test.sim/sim_1/behav/pingpang_tb_v.prj
PingPang_buffer_20160526/test.sim/sim_1/behav/pingpang_tb_v.tcl
PingPang_buffer_20160526/test.sim/sim_1/behav/pingpang_tb_v_behav.log
PingPang_buffer_20160526/test.sim/sim_1/behav/pingpang_tb_v_behav.wdb
PingPang_buffer_20160526/test.sim/sim_1/behav/xelab.log
PingPang_buffer_20160526/test.sim/sim_1/behav/xelab.pb
PingPang_buffer_20160526/test.sim/sim_1/behav/xsim.dir/blk_mem_gen_v8_0/beh_ff_ce.vdb
PingPang_buffer_20160526/test.sim/sim_1/behav/xsim.dir/blk_mem_gen_v8_0/beh_ff_clr.vdb
PingPang_buffer_20160526/test.sim/sim_1/behav/xsim.dir/blk_mem_gen_v8_0/beh_ff_pre.vdb
PingPang_buffer_20160526/test.sim/sim_1/behav/xsim.dir/blk_mem_gen_v8_0/beh_muxf7.vdb
PingPang_buffer_20160526/test.sim/sim_1/behav/xsim.dir/blk_mem_gen_v8_0/blk_mem_axi_read_wrapper_beh.vdb
PingPang_buffer_20160526/test.sim/sim_1/behav/xsim.dir/blk_mem_gen_v8_0/blk_mem_axi_regs_fwd_v8_0.vdb
PingPang_buffer_20160526/test.sim/sim_1/behav/xsim.dir/blk_mem_gen_v8_0/blk_mem_axi_write_wrapper_beh.vdb
PingPang_buffer_20160526/test.sim/sim_1/behav/xsim.dir/blk_mem_gen_v8_0/blk_mem_gen_v8_0.vdb
PingPang_buffer_20160526/test.sim/sim_1/behav/xsim.dir/blk_mem_gen_v8_0/blk_mem_gen_v8_0_mem_module.vdb
PingPang_buffer_20160526/test.sim/sim_1/behav/xsim.dir/blk_mem_gen_v8_0/blk_mem_gen_v8_0_output_stage.vdb
PingPang_buffer_20160526/test.sim/sim_1/behav/xsim.dir/blk_mem_gen_v8_0/blk_mem_gen_v8_0_softecc_output_reg_stage.vdb
PingPang_buffer_20160526/test.sim/sim_1/behav/xsim.dir/blk_mem_gen_v8_0/read_netlist.vdb
PingPang_buffer_20160526/test.sim/sim_1/behav/xsim.dir/blk_mem_gen_v8_0/state_logic.vdb
PingPang_buffer_20160526/test.sim/sim_1/behav/xsim.dir/blk_mem_gen_v8_0/write_netlist.vdb
PingPang_buffer_20160526/test.sim/sim_1/behav/xsim.dir/blk_mem_gen_v8_2/@b@l@k_@m@e@m_@g@e@n_v8_2_mem_module.sdb
PingPang_buffer_20160526/test.sim/sim_1/behav/xsim.dir/blk_mem_gen_v8_2/@b@l@k_@m@e@m_@g@e@n_v8_2_output_stage.sdb
PingPang_buffer_20160526/test.sim/sim_1/behav/xsim.dir/blk_mem_gen_v8_2/@b@l@k_@m@e@m_@g@e@n_v8_2_softecc_output_reg_stage.sdb
PingPang_buffer_20160526/test.sim/sim_1/behav/xsim.dir/blk_mem_gen_v8_2/@s@t@a@t@e_@l@o@g@i@c_v8_2.sdb
PingPang_buffer_20160526/test.sim/sim_1/behav/xsim.dir/blk_mem_gen_v8_2/beh_vlog_ff_ce_clr_v8_2.sdb
PingPang_buffer_20160526/test.sim/sim_1/behav/xsim.dir/blk_mem_gen_v8_2/beh_vlog_ff_clr_v8_2.sdb
PingPang_buffer_20160526/test.sim/sim_1/behav/xsim.dir/blk_mem_gen_v8_2/beh_vlog_ff_pre_v8_2.sdb
PingPang_buffer_20160526/test.sim/sim_1/behav/xsim.dir/blk_mem_gen_v8_2/beh_vlog_muxf7_v8_2.sdb
PingPang_buffer_20160526/test.sim/sim_1/behav/xsim.dir/blk_mem_gen_v8_2/blk_mem_axi_read_wrapper_beh_v8_2.sdb
PingPang_buffer_20160526/test.sim/sim_1/behav/xsim.dir/blk_mem_gen_v8_2/blk_mem_axi_regs_fwd_v8_2.sdb
PingPang_buffer_20160526/test.sim/sim_1/behav/xsim.dir/blk_mem_gen_v8_2/blk_mem_axi_write_wrapper_beh_v8_2.sdb
PingPang_buffer_20160526/test.sim/sim_1/behav/xsim.dir/blk_mem_gen_v8_2/blk_mem_gen_v8_2.sdb
PingPang_buffer_20160526/test.sim/sim_1/behav/xsim.dir/blk_mem_gen_v8_2/read_netlist_v8_2.sdb
PingPang_buffer_20160526/test.sim/sim_1/behav/xsim.dir/blk_mem_gen_v8_2/write_netlist_v8_2.sdb
PingPang_buffer_20160526/test.sim/sim_1/behav/xsim.dir/fifo_generator_v10_0/@f@i@f@o_@g@e@n@e@r@a@t@o@r_@v10_0_@c@o@n@v_@v@e@r.sdb
PingPang_buffer_20160526/test.sim/sim_1/behav/xsim.dir/fifo_generator_v10_0/fifo_generator_v10_0.sdb
PingPang_buffer_20160526/test.sim/sim_1/behav/xsim.dir/fifo_generator_v10_0/fifo_generator_v10_0_axic_reg_slice.sdb
PingPang_buffer_20160526/test.sim/sim_1/behav/xsim.dir/fifo_generator_v10_0/fifo_generator_v10_0_beh_ver_ll_afifo.sdb
PingPang_buffer_20160526/test.sim/sim_1/behav/xsim.dir/fifo_generator_v10_0/fifo_generator_v10_0_bhv_ver_as.sdb
PingPang_buffer_20160526/test.sim/sim_1/behav/xsim.dir/fifo_generator_v10_0/fifo_generator_v10_0_bhv_ver_preload0.sdb
PingPang_buffer_20160526/test.sim/sim_1/behav/xsim.dir/fifo_generator_v10_0/fifo_generator_v10_0_bhv_ver_ss.sdb
PingPang_buffer_20160526/test.sim/sim_1/behav/xsim.dir/fifo_generator_v10_0/fifo_generator_v10_0_sync_stage.sdb
PingPang_buffer_20160526/test.sim/sim_1/behav/xsim.dir/pingpang_tb_v_behav/Compile_Options.

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