随着工艺线宽的减小, 时序问题开始主导集成电路设计。为了解决全芯片的互连延时, 需

要全芯片分析和优化:

Pr im eT im e 是S yn oP sys 公司全芯片和门级静态时序分析工具。

Pr im eTi m e 用来分

析大型同步数字专用集成电路

。

静态时序分析是一种彻底的分析、调试、验证设计的方法-With the reduced width of the process, timing issues began to dominate the IC design. In order to solve the interconnect delay full-chip, full-chip analysis and optimization needs: Pr im eT im e S yn oP sys is a wholly-chip and gate-level static timing analysis tools. Pr im eTi me to analyze large synchronous digital ASIC. Static timing analysis is a thorough analysis, debug, verification, design methods