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文件名称:09_SDRAM_VGA_Display_Test640480

  • 所属分类：
    VHDL-FPGA-Verilog
  • 标签属性：
    [C/C++] [源码]
  • 上传时间：
    2016-07-07
  • 文件大小：
    322.21kb
  • 已下载：
    1次
  • 提 供 者：
    郑****
  • 相关连接：
    无
  • 下载说明：
    别用迅雷下载，失败请重下，重下不扣分！
修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

在quartusII的开发环境下，编写的VerilogHDL语言的SDRAM通信程序，欢迎下载，这是基于Crazybingo的板卡环境设计-Under the development environment of quartusII, write SDRAM VerilogHDL language communication program, welcome to download, this is based on Crazybingo board environment design
(系统自动生成,下载前可以参看下载内容)

下载文件列表

09_SDRAM_VGA_Display_Test640480/core/sdram_pll.bsf
09_SDRAM_VGA_Display_Test640480/core/sdram_pll.ppf
09_SDRAM_VGA_Display_Test640480/core/sdram_pll.qip
09_SDRAM_VGA_Display_Test640480/core/sdram_pll.v
09_SDRAM_VGA_Display_Test640480/dev/output_files/greybox_tmp/cbx_args.txt
09_SDRAM_VGA_Display_Test640480/dev/output_files/read_fifo1.qip
09_SDRAM_VGA_Display_Test640480/dev/output_files/SDRAM_VGA_Display_Test.asm.rpt
09_SDRAM_VGA_Display_Test640480/dev/output_files/SDRAM_VGA_Display_Test.cdf
09_SDRAM_VGA_Display_Test640480/dev/output_files/SDRAM_VGA_Display_Test.done
09_SDRAM_VGA_Display_Test640480/dev/output_files/SDRAM_VGA_Display_Test.fit.rpt
09_SDRAM_VGA_Display_Test640480/dev/output_files/SDRAM_VGA_Display_Test.fit.smsg
09_SDRAM_VGA_Display_Test640480/dev/output_files/SDRAM_VGA_Display_Test.fit.summary
09_SDRAM_VGA_Display_Test640480/dev/output_files/SDRAM_VGA_Display_Test.flow.rpt
09_SDRAM_VGA_Display_Test640480/dev/output_files/SDRAM_VGA_Display_Test.jdi
09_SDRAM_VGA_Display_Test640480/dev/output_files/SDRAM_VGA_Display_Test.map.rpt
09_SDRAM_VGA_Display_Test640480/dev/output_files/SDRAM_VGA_Display_Test.map.smsg
09_SDRAM_VGA_Display_Test640480/dev/output_files/SDRAM_VGA_Display_Test.map.summary
09_SDRAM_VGA_Display_Test640480/dev/output_files/SDRAM_VGA_Display_Test.pin
09_SDRAM_VGA_Display_Test640480/dev/output_files/SDRAM_VGA_Display_Test.sof
09_SDRAM_VGA_Display_Test640480/dev/output_files/SDRAM_VGA_Display_Test.sta.rpt
09_SDRAM_VGA_Display_Test640480/dev/output_files/SDRAM_VGA_Display_Test.sta.summary
09_SDRAM_VGA_Display_Test640480/dev/output_files/sys_pll.qip
09_SDRAM_VGA_Display_Test640480/dev/output_files/write_fifo1.qip
09_SDRAM_VGA_Display_Test640480/dev/PLLJ_PLLSPE_INFO.txt
09_SDRAM_VGA_Display_Test640480/dev/read_fifo1.qip
09_SDRAM_VGA_Display_Test640480/dev/SDRAM_VGA_Display_Test.qpf
09_SDRAM_VGA_Display_Test640480/dev/SDRAM_VGA_Display_Test.qsf
09_SDRAM_VGA_Display_Test640480/dev/SDRAM_VGA_Display_Test.qws
09_SDRAM_VGA_Display_Test640480/dev/SDRAM_VGA_Display_Test.tcl
09_SDRAM_VGA_Display_Test640480/dev/SDRAM_VGA_Display_Test.tcl.bak
09_SDRAM_VGA_Display_Test640480/dev/sys_pll.qip
09_SDRAM_VGA_Display_Test640480/dev/VIP_System.sdc
09_SDRAM_VGA_Display_Test640480/dev/VIP_System.sdc.bak
09_SDRAM_VGA_Display_Test640480/src/Camera_ISP_Design.v.bak
09_SDRAM_VGA_Display_Test640480/src/lcd_24bit_ip/lcd_display.v
09_SDRAM_VGA_Display_Test640480/src/lcd_24bit_ip/lcd_display.v.bak
09_SDRAM_VGA_Display_Test640480/src/lcd_24bit_ip/lcd_driver.v
09_SDRAM_VGA_Display_Test640480/src/lcd_24bit_ip/lcd_driver.v.bak
09_SDRAM_VGA_Display_Test640480/src/lcd_24bit_ip/lcd_driver_zoom.v
09_SDRAM_VGA_Display_Test640480/src/lcd_24bit_ip/lcd_driver_zoom.v.bak
09_SDRAM_VGA_Display_Test640480/src/lcd_24bit_ip/lcd_para.v
09_SDRAM_VGA_Display_Test640480/src/lcd_24bit_ip/lcd_para.v.bak
09_SDRAM_VGA_Display_Test640480/src/lcd_24bit_ip/read_fifo1.qip
09_SDRAM_VGA_Display_Test640480/src/lcd_24bit_ip/sys_pll.qip
09_SDRAM_VGA_Display_Test640480/src/lcd_24bit_ip/VGAData_Simulate_24Bit.v
09_SDRAM_VGA_Display_Test640480/src/lcd_24bit_ip/VGAData_Simulate_24Bit.v.bak
09_SDRAM_VGA_Display_Test640480/src/lcd_24bit_ip/write_fifo1.qip
09_SDRAM_VGA_Display_Test640480/src/Sdram_Control_2Port_1MX32Bit/command.v
09_SDRAM_VGA_Display_Test640480/src/Sdram_Control_2Port_1MX32Bit/command.v.bak
09_SDRAM_VGA_Display_Test640480/src/Sdram_Control_2Port_1MX32Bit/control_interface.v
09_SDRAM_VGA_Display_Test640480/src/Sdram_Control_2Port_1MX32Bit/control_interface.v.bak
09_SDRAM_VGA_Display_Test640480/src/Sdram_Control_2Port_1MX32Bit/read_fifo1.bsf
09_SDRAM_VGA_Display_Test640480/src/Sdram_Control_2Port_1MX32Bit/read_fifo1.qip
09_SDRAM_VGA_Display_Test640480/src/Sdram_Control_2Port_1MX32Bit/read_fifo1.v
09_SDRAM_VGA_Display_Test640480/src/Sdram_Control_2Port_1MX32Bit/read_fifo1.v.bak
09_SDRAM_VGA_Display_Test640480/src/Sdram_Control_2Port_1MX32Bit/read_fifo1_wave0.jpg
09_SDRAM_VGA_Display_Test640480/src/Sdram_Control_2Port_1MX32Bit/read_fifo1_waveforms.html
09_SDRAM_VGA_Display_Test640480/src/Sdram_Control_2Port_1MX32Bit/Sdram_Control_2Port.v
09_SDRAM_VGA_Display_Test640480/src/Sdram_Control_2Port_1MX32Bit/Sdram_Control_2Port.v.bak
09_SDRAM_VGA_Display_Test640480/src/Sdram_Control_2Port_1MX32Bit/Sdram_Params.h
09_SDRAM_VGA_Display_Test640480/src/Sdram_Control_2Port_1MX32Bit/Sdram_Params.h.bak
09_SDRAM_VGA_Display_Test640480/src/Sdram_Control_2Port_1MX32Bit/sdr_data_path.v.bak
09_SDRAM_VGA_Display_Test640480/src/Sdram_Control_2Port_1MX32Bit/write_fifo1.bsf
09_SDRAM_VGA_Display_Test640480/src/Sdram_Control_2Port_1MX32Bit/write_fifo1.qip
09_SDRAM_VGA_Display_Test640480/src/Sdram_Control_2Port_1MX32Bit/write_fifo1.v
09_SDRAM_VGA_Display_Test640480/src/Sdram_Control_2Port_1MX32Bit/write_fifo1.v.bak
09_SDRAM_VGA_Display_Test640480/src/Sdram_Control_2Port_1MX32Bit/write_fifo1_wave0.jpg
09_SDRAM_VGA_Display_Test640480/src/Sdram_Control_2Port_1MX32Bit/write_fifo1_waveforms.html
09_SDRAM_VGA_Display_Test640480/src/SDRAM_VGA_Display_Test.v
09_SDRAM_VGA_Display_Test640480/src/SDRAM_VGA_Display_Test.v.bak
09_SDRAM_VGA_Display_Test640480/src/system_index/system_ctrl.v
09_SDRAM_VG

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