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文件名称:CD1_PHOTO_ABLUM_1920

  • 所属分类：
    VHDL-FPGA-Verilog
  • 标签属性：
    [MacOS] [C/C++] [源码]
  • 上传时间：
    2016-07-13
  • 文件大小：
    3.73mb
  • 已下载：
    0次
  • 提 供 者：
    丁**
  • 相关连接：
    无
  • 下载说明：
    别用迅雷下载，失败请重下，重下不扣分！
修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

使用FPGA做的数码相册实验，用NIOS做了FAT32文件系统和JPEG图像解码,FPGA和SDRAM做了显示的缓存-Using FPGA to do the digital album experiment, using NIOS to do the FAT32 file system and JPEG image decoding, FPGA and SDRAM to do the display cache
(系统自动生成,下载前可以参看下载内容)

下载文件列表

CD1_PHOTO_ABLUM_1920/FPGA/.qsys_edit/filters.xml
CD1_PHOTO_ABLUM_1920/FPGA/.qsys_edit/preferences.xml
CD1_PHOTO_ABLUM_1920/FPGA/.sopc_builder/filters.xml
CD1_PHOTO_ABLUM_1920/FPGA/.sopc_builder/install.ptf
CD1_PHOTO_ABLUM_1920/FPGA/.sopc_builder/install2.ptf
CD1_PHOTO_ABLUM_1920/FPGA/.sopc_builder/preferences.xml
CD1_PHOTO_ABLUM_1920/FPGA/CD1_PHOTO_ABLUM_1920.asm.rpt
CD1_PHOTO_ABLUM_1920/FPGA/CD1_PHOTO_ABLUM_1920.cdf
CD1_PHOTO_ABLUM_1920/FPGA/CD1_PHOTO_ABLUM_1920.done
CD1_PHOTO_ABLUM_1920/FPGA/CD1_PHOTO_ABLUM_1920.dpf
CD1_PHOTO_ABLUM_1920/FPGA/CD1_PHOTO_ABLUM_1920.fit.rpt
CD1_PHOTO_ABLUM_1920/FPGA/CD1_PHOTO_ABLUM_1920.fit.smsg
CD1_PHOTO_ABLUM_1920/FPGA/CD1_PHOTO_ABLUM_1920.fit.summary
CD1_PHOTO_ABLUM_1920/FPGA/CD1_PHOTO_ABLUM_1920.flow.rpt
CD1_PHOTO_ABLUM_1920/FPGA/CD1_PHOTO_ABLUM_1920.jdi
CD1_PHOTO_ABLUM_1920/FPGA/CD1_PHOTO_ABLUM_1920.map.rpt
CD1_PHOTO_ABLUM_1920/FPGA/CD1_PHOTO_ABLUM_1920.map.smsg
CD1_PHOTO_ABLUM_1920/FPGA/CD1_PHOTO_ABLUM_1920.map.summary
CD1_PHOTO_ABLUM_1920/FPGA/CD1_PHOTO_ABLUM_1920.pin
CD1_PHOTO_ABLUM_1920/FPGA/CD1_PHOTO_ABLUM_1920.pof
CD1_PHOTO_ABLUM_1920/FPGA/CD1_PHOTO_ABLUM_1920.qpf
CD1_PHOTO_ABLUM_1920/FPGA/CD1_PHOTO_ABLUM_1920.qsf
CD1_PHOTO_ABLUM_1920/FPGA/CD1_PHOTO_ABLUM_1920.sdc
CD1_PHOTO_ABLUM_1920/FPGA/CD1_PHOTO_ABLUM_1920.sof
CD1_PHOTO_ABLUM_1920/FPGA/CD1_PHOTO_ABLUM_1920.sta.rpt
CD1_PHOTO_ABLUM_1920/FPGA/CD1_PHOTO_ABLUM_1920.sta.summary
CD1_PHOTO_ABLUM_1920/FPGA/CD1_PHOTO_ABLUM_1920.v
CD1_PHOTO_ABLUM_1920/FPGA/CF.v
CD1_PHOTO_ABLUM_1920/FPGA/cf_0.v
CD1_PHOTO_ABLUM_1920/FPGA/CONTROL.v
CD1_PHOTO_ABLUM_1920/FPGA/cpu_0.ocp
CD1_PHOTO_ABLUM_1920/FPGA/cpu_0.sdc
CD1_PHOTO_ABLUM_1920/FPGA/cpu_0.v
CD1_PHOTO_ABLUM_1920/FPGA/cpu_0_bht_ram.mif
CD1_PHOTO_ABLUM_1920/FPGA/cpu_0_dc_tag_ram.mif
CD1_PHOTO_ABLUM_1920/FPGA/cpu_0_ic_tag_ram.mif
CD1_PHOTO_ABLUM_1920/FPGA/cpu_0_jtag_debug_module_sysclk.v
CD1_PHOTO_ABLUM_1920/FPGA/cpu_0_jtag_debug_module_tck.v
CD1_PHOTO_ABLUM_1920/FPGA/cpu_0_jtag_debug_module_wrapper.v
CD1_PHOTO_ABLUM_1920/FPGA/cpu_0_mult_cell.v
CD1_PHOTO_ABLUM_1920/FPGA/cpu_0_ociram_default_contents.mif
CD1_PHOTO_ABLUM_1920/FPGA/cpu_0_oci_test_bench.v
CD1_PHOTO_ABLUM_1920/FPGA/cpu_0_rf_ram_a.mif
CD1_PHOTO_ABLUM_1920/FPGA/cpu_0_rf_ram_b.mif
CD1_PHOTO_ABLUM_1920/FPGA/cpu_0_test_bench.v
CD1_PHOTO_ABLUM_1920/FPGA/epcs_flash_controller_0.v
CD1_PHOTO_ABLUM_1920/FPGA/epcs_flash_controller_0_boot_rom.hex
CD1_PHOTO_ABLUM_1920/FPGA/epcs_flash_controller_0_boot_rom_synth.hex
CD1_PHOTO_ABLUM_1920/FPGA/Image_RW_0.v
CD1_PHOTO_ABLUM_1920/FPGA/IP/Image_RW/Image_RW.v
CD1_PHOTO_ABLUM_1920/FPGA/IP/Image_RW/Image_RW_hw.tcl
CD1_PHOTO_ABLUM_1920/FPGA/IP/Image_RW/Image_RW_hw.tcl~
CD1_PHOTO_ABLUM_1920/FPGA/IP/SRAM_16Bit_512K/hdl/SRAM_16Bit_512K.v
CD1_PHOTO_ABLUM_1920/FPGA/IP/SRAM_16Bit_512K/SRAM_16Bit_512K_hw.tcl
CD1_PHOTO_ABLUM_1920/FPGA/jtag_uart_0.v
CD1_PHOTO_ABLUM_1920/FPGA/KEY.v
CD1_PHOTO_ABLUM_1920/FPGA/LED.v
CD1_PHOTO_ABLUM_1920/FPGA/nios.bsf
CD1_PHOTO_ABLUM_1920/FPGA/nios.html
CD1_PHOTO_ABLUM_1920/FPGA/nios.ptf
CD1_PHOTO_ABLUM_1920/FPGA/nios.ptf.8.0
CD1_PHOTO_ABLUM_1920/FPGA/nios.ptf.pre_generation_ptf
CD1_PHOTO_ABLUM_1920/FPGA/nios.qip
CD1_PHOTO_ABLUM_1920/FPGA/nios.sopc
CD1_PHOTO_ABLUM_1920/FPGA/nios.sopcinfo
CD1_PHOTO_ABLUM_1920/FPGA/nios.v
CD1_PHOTO_ABLUM_1920/FPGA/nios_generation_script
CD1_PHOTO_ABLUM_1920/FPGA/nios_inst.v
CD1_PHOTO_ABLUM_1920/FPGA/nios_log.txt
CD1_PHOTO_ABLUM_1920/FPGA/nios_sim/atail-f.pl
CD1_PHOTO_ABLUM_1920/FPGA/nios_sim/dummy_file
CD1_PHOTO_ABLUM_1920/FPGA/nios_sim/jtag_uart_0_input_mutex.dat
CD1_PHOTO_ABLUM_1920/FPGA/nios_sim/jtag_uart_0_input_stream.dat
CD1_PHOTO_ABLUM_1920/FPGA/nios_sim/jtag_uart_0_output_stream.dat
CD1_PHOTO_ABLUM_1920/FPGA/nios_upgrade_log.txt
CD1_PHOTO_ABLUM_1920/FPGA/PIO.v
CD1_PHOTO_ABLUM_1920/FPGA/PLL108.ppf
CD1_PHOTO_ABLUM_1920/FPGA/PLL108.qip
CD1_PHOTO_ABLUM_1920/FPGA/PLL108.v
CD1_PHOTO_ABLUM_1920/FPGA/PLL50.ppf
CD1_PHOTO_ABLUM_1920/FPGA/PLL50.qip
CD1_PHOTO_ABLUM_1920/FPGA/PLL50.v
CD1_PHOTO_ABLUM_1920/FPGA/PLLJ_PLLSPE_INFO.txt
CD1_PHOTO_ABLUM_1920/FPGA/sdram_0.v
CD1_PHOTO_ABLUM_1920/FPGA/Sdram_FIFO.qip
CD1_PHOTO_ABLUM_1920/FPGA/Sdram_PLL.qip
CD1_PHOTO_ABLUM_1920/FPGA/sopc_add_qip_file.tcl
CD1_PHOTO_ABLUM_1920/FPGA/sopc_builder_log.txt
CD1_PHOTO_ABLUM_1920/FPGA/SPI_CONFIG.v
CD1_PHOTO_ABLUM_1920/FPGA/SPI_MASTER.v
CD1_PHOTO_ABLUM_1920/FPGA/SRAM.v
CD1_PHOTO_ABLUM_1920/FPGA/sram0.v
CD1_PHOTO_ABLUM_1920/FPGA/SRAM_16Bit_512K_0.v
CD1_PHOTO_ABLUM_1920/FPGA/timer_0.v
CD1_PHOTO_ABLUM_1920/FPGA/USER_CODE/Reset_Delay.v
CD1_PHOTO_ABLUM_1920/FPGA/USER_CODE/Sdram_Control_4Port/command.v
CD1_PHOTO_ABLUM_1920/FPGA/USER_CODE/Sdram_Control_4Port/control_interface.v
CD1_PHOTO_ABLUM_1920/FPGA/USER_CODE/Sdram_Control_4Port/Sdram_Control_4Port.v
CD1_PHOTO_ABLUM_1920/FPGA/USER_CODE/Sdram_Control_4Port/Sdram_FIFO.qip
CD1_PHOTO_ABLUM_1920/FPGA/USER_CODE/Sdram_Control_4Port/Sdram_FIFO.v
CD1_PHOTO_ABLUM_1920/FPGA/USER_CODE/Sdram_Control_4Port/Sdram_Params.h
CD1_PHOTO_ABLUM_1920/FPGA/USER_CODE/Sdram_Control_4Port/Sdram_PLL.ppf
CD1_PHOTO_ABLUM_1920/FPGA/USER_CODE/Sdram_Control_4Port/Sdram_PLL.qip
CD1_PHOTO_ABLUM_1920/FPGA/USER_CODE/Sdram_Control_4Port/Sdram_PLL.v
CD1_PHOTO_ABLUM_1920/FPGA/USER_

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