最新修改 veilog 除法器，32位除16位，输出数据锁存-//divider　dividend　 divisor* quotient+ remainder

//dividend　32 bit

//divisor　 16 bit

//quotient　32 bit

//remainder 32 bit

//need 32 clk to finish the calculation

//start　 1 start the calculation

//start　 0 keep the reset

//when finished, sample　 1, and the result will be keep until start 0