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文件名称:sine

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    2008-10-13
  • 文件大小:
    3.4mb
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    1次
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介绍说明--下载内容来自于网络,使用问题请自行百度

用VerilogHDL实现的产生Sine波形全部程序

个人验证后收藏的。
(系统自动生成,下载前可以参看下载内容)

下载文件列表

sine/altera_mf.v
sine/cycloneii_atoms.v
sine/db/ram0_rom16x7_5ff456ad.hdl.mif
sine/db/sine.(0).cnf.cdb
sine/db/sine.(0).cnf.hdb
sine/db/sine.(1).cnf.cdb
sine/db/sine.(1).cnf.hdb
sine/db/sine.asm.qmsg
sine/db/sine.asm_labs.ddb
sine/db/sine.cbx.xml
sine/db/sine.cmp.bpm
sine/db/sine.cmp.cdb
sine/db/sine.cmp.ecobp
sine/db/sine.cmp.hdb
sine/db/sine.cmp.logdb
sine/db/sine.cmp.rdb
sine/db/sine.cmp.tdb
sine/db/sine.cmp0.ddb
sine/db/sine.cmp_bb.cdb
sine/db/sine.cmp_bb.hdb
sine/db/sine.cmp_bb.logdb
sine/db/sine.cmp_bb.rcf
sine/db/sine.dbp
sine/db/sine.db_info
sine/db/sine.eco.cdb
sine/db/sine.eda.qmsg
sine/db/sine.fit.qmsg
sine/db/sine.hier_info
sine/db/sine.hif
sine/db/sine.map.bpm
sine/db/sine.map.cdb
sine/db/sine.map.ecobp
sine/db/sine.map.hdb
sine/db/sine.map.logdb
sine/db/sine.map.qmsg
sine/db/sine.map_bb.cdb
sine/db/sine.map_bb.hdb
sine/db/sine.map_bb.logdb
sine/db/sine.pre_map.cdb
sine/db/sine.pre_map.hdb
sine/db/sine.psp
sine/db/sine.pss
sine/db/sine.rtlv.hdb
sine/db/sine.rtlv_sg.cdb
sine/db/sine.rtlv_sg_swap.cdb
sine/db/sine.sgdiff.cdb
sine/db/sine.sgdiff.hdb
sine/db/sine.signalprobe.cdb
sine/db/sine.sld_design_entry.sci
sine/db/sine.sld_design_entry_dsc.sci
sine/db/sine.syn_hier_info
sine/db/sine.tan.qmsg
sine/db/sine.tis_db_list.ddb
sine/db
sine/ROM.DAT
sine/rom16x7.v
sine/simulation/modelsim/sine.vo
sine/simulation/modelsim/sine_modelsim.xrf
sine/simulation/modelsim/sine_v.sdo
sine/simulation/modelsim
sine/simulation
sine/sine.asm.rpt
sine/sine.done
sine/sine.eda.rpt
sine/sine.fit.rpt
sine/sine.fit.smsg
sine/sine.fit.summary
sine/sine.flow.rpt
sine/sine.map.rpt
sine/sine.map.summary
sine/sine.pin
sine/sine.pof
sine/sine.qpf
sine/sine.qsf
sine/sine.qws
sine/sine.sof
sine/sine.tan.rpt
sine/sine.tan.summary
sine/sine.v
sine/sine.vo
sine/sinetest.v
sine/sine_test/altera_mf.v
sine/sine_test/cycloneii_atoms.v
sine/sine_test/sine.cr.mti
sine/sine_test/sine.mpf
sine/sine_test/sine.vo
sine/sine_test/sinetest.v
sine/sine_test/sinetest.v.bak
sine/sine_test/sine_v.sdo
sine/sine_test/vsim.wlf
sine/sine_test/work/@a@l@t@e@r@a_@d@e@v@i@c@e_@f@a@m@i@l@i@e@s/verilog.asm
sine/sine_test/work/@a@l@t@e@r@a_@d@e@v@i@c@e_@f@a@m@i@l@i@e@s/_primary.dat
sine/sine_test/work/@a@l@t@e@r@a_@d@e@v@i@c@e_@f@a@m@i@l@i@e@s/_primary.vhd
sine/sine_test/work/@a@l@t@e@r@a_@d@e@v@i@c@e_@f@a@m@i@l@i@e@s
sine/sine_test/work/@a@l@t@e@r@a_@m@f_@h@i@n@t_@e@v@a@l@u@a@t@i@o@n/verilog.asm
sine/sine_test/work/@a@l@t@e@r@a_@m@f_@h@i@n@t_@e@v@a@l@u@a@t@i@o@n/_primary.dat
sine/sine_test/work/@a@l@t@e@r@a_@m@f_@h@i@n@t_@e@v@a@l@u@a@t@i@o@n/_primary.vhd
sine/sine_test/work/@a@l@t@e@r@a_@m@f_@h@i@n@t_@e@v@a@l@u@a@t@i@o@n
sine/sine_test/work/@a@l@t@e@r@a_@m@f_@m@e@m@o@r@y_@i@n@i@t@i@a@l@i@z@a@t@i@o@n/verilog.asm
sine/sine_test/work/@a@l@t@e@r@a_@m@f_@m@e@m@o@r@y_@i@n@i@t@i@a@l@i@z@a@t@i@o@n/_primary.dat
sine/sine_test/work/@a@l@t@e@r@a_@m@f_@m@e@m@o@r@y_@i@n@i@t@i@a@l@i@z@a@t@i@o@n/_primary.vhd
sine/sine_test/work/@a@l@t@e@r@a_@m@f_@m@e@m@o@r@y_@i@n@i@t@i@a@l@i@z@a@t@i@o@n
sine/sine_test/work/@c@y@c@l@o@n@e@i@i_@p@r@i@m_@d@f@f@e/verilog.asm
sine/sine_test/work/@c@y@c@l@o@n@e@i@i_@p@r@i@m_@d@f@f@e/_primary.dat
sine/sine_test/work/@c@y@c@l@o@n@e@i@i_@p@r@i@m_@d@f@f@e/_primary.vhd
sine/sine_test/work/@c@y@c@l@o@n@e@i@i_@p@r@i@m_@d@f@f@e
sine/sine_test/work/@m@f_cycloneiii_pll/verilog.asm
sine/sine_test/work/@m@f_cycloneiii_pll/_primary.dat
sine/sine_test/work/@m@f_cycloneiii_pll/_primary.vhd
sine/sine_test/work/@m@f_cycloneiii_pll
sine/sine_test/work/@m@f_pll_reg/verilog.asm
sine/sine_test/work/@m@f_pll_reg/_primary.dat
sine/sine_test/work/@m@f_pll_reg/_primary.vhd
sine/sine_test/work/@m@f_pll_reg
sine/sine_test/work/@m@f_ram7x20_syn/verilog.asm
sine/sine_test/work/@m@f_ram7x20_syn/_primary.dat
sine/sine_test/work/@m@f_ram7x20_syn/_primary.vhd
sine/sine_test/work/@m@f_ram7x20_syn
sine/sine_test/work/@m@f_stratixiii_pll/verilog.asm
sine/sine_test/work/@m@f_stratixiii_pll/_primary.dat
sine/sine_test/work/@m@f_stratixiii_pll/_primary.vhd
sine/sine_test/work/@m@f_stratixiii_pll
sine/sine_test/work/@m@f_stratixii_pll/verilog.asm
sine/sine_test/work/@m@f_stratixii_pll/_primary.dat
sine/sine_test/work/@m@f_stratixii_pll/_primary.vhd
sine/sine_test/work/@m@f_stratixii_pll
sine/sine_test/work/@m@f_stratix_pll/verilog.asm
sine/sine_test/work/@m@f_stratix_pll/_primary.dat
sine/sine_test/work/@m@f_stratix_pll/_primary.vhd
sine/sine_test/work/@m@f_stratix_pll
sine/sine_test/work/alt3pram/verilog.asm
sine/sine_test/work/alt3pram/_primary.dat
sine/sine_test/work/alt3pram/_primary.vhd
sine/sine_test/work/alt3pram
sine/sine_test/work/altaccumulate/verilog.asm
sine/sine_test/work/altaccumulate/_primary.dat
sine/sine_test/work/altaccumulate/_primary.vhd
sine/sine_test/work/altaccumulate
sine/sine_test/work/altcam/verilog.asm
sine/sine_test/work/altcam/_primary.dat
sine/sine_test/work/altcam/_primary.vhd
sine/sine_test/work/altcam
sine/sine_test/work/altcdr_rx/verilog.asm
sine/sine_test/work/altcdr_rx/_primary.dat
sine/sine_test/work/altcdr_rx/_primary.vhd
sine/sine_test/work/altcdr_rx
sine/sine_test/work/altcdr_tx/verilog.asm
sine/sine_test/work/altcdr_tx/_primary.dat
sine/sine_test/work/altcdr_tx/

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