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文件名称:cpld

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  • 上传时间:
    2016-09-14
  • 文件大小:
    217.93kb
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介绍说明--下载内容来自于网络,使用问题请自行百度

使用cpld完成多个串口切换通信,能够完成快速通信,已经完成验证-Using CPLD to complete multiple serial communication
(系统自动生成,下载前可以参看下载内容)

下载文件列表

cpld/
cpld/db/
cpld/db/epm3032a.(0).cnf.cdb
cpld/db/epm3032a.(0).cnf.hdb
cpld/db/epm3032a.(1).cnf.cdb
cpld/db/epm3032a.(1).cnf.hdb
cpld/db/epm3032a.asm.qmsg
cpld/db/epm3032a.asm.rdb
cpld/db/epm3032a.cbx.xml
cpld/db/epm3032a.cmp.cdb
cpld/db/epm3032a.cmp.hdb
cpld/db/epm3032a.cmp.logdb
cpld/db/epm3032a.cmp.rdb
cpld/db/epm3032a.cmp0.ddb
cpld/db/epm3032a.db_info
cpld/db/epm3032a.eda.qmsg
cpld/db/epm3032a.fit.qmsg
cpld/db/epm3032a.hier_info
cpld/db/epm3032a.hif
cpld/db/epm3032a.lpc.html
cpld/db/epm3032a.lpc.rdb
cpld/db/epm3032a.lpc.txt
cpld/db/epm3032a.map.cdb
cpld/db/epm3032a.map.hdb
cpld/db/epm3032a.map.logdb
cpld/db/epm3032a.map.qmsg
cpld/db/epm3032a.pre_map.cdb
cpld/db/epm3032a.pre_map.hdb
cpld/db/epm3032a.rtlv.hdb
cpld/db/epm3032a.rtlv_sg.cdb
cpld/db/epm3032a.rtlv_sg_swap.cdb
cpld/db/epm3032a.sgdiff.cdb
cpld/db/epm3032a.sgdiff.hdb
cpld/db/epm3032a.sld_design_entry.sci
cpld/db/epm3032a.sld_design_entry_dsc.sci
cpld/db/epm3032a.smart_action.txt
cpld/db/epm3032a.sta.qmsg
cpld/db/epm3032a.sta.rdb
cpld/db/epm3032a.sta_cmp.10_slow.tdb
cpld/db/epm3032a.syn_hier_info
cpld/db/epm3032a.tis_db_list.ddb
cpld/db/epm3032a.tmw_info
cpld/db/logic_util_heursitic.dat
cpld/db/prev_cmp_epm3032a.qmsg
cpld/epm3032a.asm.rpt
cpld/epm3032a.cdf
cpld/epm3032a.done
cpld/epm3032a.eda.rpt
cpld/epm3032a.fit.rpt
cpld/epm3032a.fit.summary
cpld/epm3032a.flow.rpt
cpld/epm3032a.map.rpt
cpld/epm3032a.map.summary
cpld/epm3032a.pin
cpld/epm3032a.pof
cpld/epm3032a.qpf
cpld/epm3032a.qsf
cpld/epm3032a.qws
cpld/epm3032a.sta.rpt
cpld/epm3032a.sta.summary
cpld/epm3032a.v
cpld/epm3032a_assignment_defaults.qdf
cpld/epm3032a_nativelink_simulation.rpt
cpld/epm3032a_v1.v
cpld/epm3032a_v1.v.bak
cpld/epm3032a_v2.v
cpld/epm3032a_v2.v.bak
cpld/epm3032a_v3.v
cpld/epm3032a_v3.v.bak
cpld/incremental_db/
cpld/incremental_db/compiled_partitions/
cpld/incremental_db/compiled_partitions/epm3032a.db_info
cpld/incremental_db/compiled_partitions/epm3032a.root_partition.map.kpt
cpld/incremental_db/README
cpld/simulation/
cpld/simulation/modelsim/
cpld/simulation/modelsim/epm3032a.sft
cpld/simulation/modelsim/epm3032a.vo
cpld/simulation/modelsim/epm3032a_modelsim.xrf
cpld/simulation/modelsim/epm3032a_run_msim_gate_verilog.do
cpld/simulation/modelsim/epm3032a_run_msim_gate_verilog.do.bak
cpld/simulation/modelsim/epm3032a_run_msim_rtl_verilog.do
cpld/simulation/modelsim/epm3032a_run_msim_rtl_verilog.do.bak
cpld/simulation/modelsim/epm3032a_run_msim_rtl_verilog.do.bak1
cpld/simulation/modelsim/epm3032a_v.sdo
cpld/simulation/modelsim/epm3032a_v.sdo_typ.csd
cpld/simulation/modelsim/gate_work/
cpld/simulation/modelsim/gate_work/epm3032a_v2/
cpld/simulation/modelsim/gate_work/epm3032a_v2/verilog.prw
cpld/simulation/modelsim/gate_work/epm3032a_v2/verilog.psm
cpld/simulation/modelsim/gate_work/epm3032a_v2/_primary.dat
cpld/simulation/modelsim/gate_work/epm3032a_v2/_primary.dbs
cpld/simulation/modelsim/gate_work/epm3032a_v2/_primary.vhd
cpld/simulation/modelsim/gate_work/testbench/
cpld/simulation/modelsim/gate_work/testbench/verilog.prw
cpld/simulation/modelsim/gate_work/testbench/verilog.psm
cpld/simulation/modelsim/gate_work/testbench/_primary.dat
cpld/simulation/modelsim/gate_work/testbench/_primary.dbs
cpld/simulation/modelsim/gate_work/testbench/_primary.vhd
cpld/simulation/modelsim/gate_work/_info
cpld/simulation/modelsim/gate_work/_temp/
cpld/simulation/modelsim/gate_work/_vmake
cpld/simulation/modelsim/modelsim.ini
cpld/simulation/modelsim/msim_transcript
cpld/simulation/modelsim/rtl_work/
cpld/simulation/modelsim/rtl_work/epm3032a_v2/
cpld/simulation/modelsim/rtl_work/epm3032a_v2/verilog.prw
cpld/simulation/modelsim/rtl_work/epm3032a_v2/verilog.psm
cpld/simulation/modelsim/rtl_work/epm3032a_v2/_primary.dat
cpld/simulation/modelsim/rtl_work/epm3032a_v2/_primary.dbs
cpld/simulation/modelsim/rtl_work/epm3032a_v2/_primary.vhd
cpld/simulation/modelsim/rtl_work/testbench/
cpld/simulation/modelsim/rtl_work/testbench/verilog.prw
cpld/simulation/modelsim/rtl_work/testbench/verilog.psm
cpld/simulation/modelsim/rtl_work/testbench/_primary.dat
cpld/simulation/modelsim/rtl_work/testbench/_primary.dbs
cpld/simulation/modelsim/rtl_work/testbench/_primary.vhd
cpld/simulation/modelsim/rtl_work/_info
cpld/simulation/modelsim/rtl_work/_temp/
cpld/simulation/modelsim/rtl_work/_vmake
cpld/simulation/modelsim/vsim.wlf
cpld/testbench.v
cpld/testbench.v.bak

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