对于FPGA状态机的设计心得

对于FPGA状态机的设计分为两类，分为mealy状态机和Moore状态机，mealy状态机的输出不仅与当前输入有关还与当前状态有关，而Moore状态机的输出仅与当前状态有关。对于状态机描述首先要知道输入，输出，当前状态，下一个状态的基本定义。

对不状态机的设计，首先要有一个初始状态，一般命名为IDLE，其状态一般设定在复位信号到来时。

对于时钟敏感的信号，在其最大的一个时钟周期作为总的状态循环，最下的一个时钟信号最为一个状态指令，一般用于时序图的描述；对于非时钟敏感的信号，对于每一个当前工作状态的判断，一般用于控制的描述。对于时序图的描述，其类似于对于过程的控制，相比于C语言；而对于控制的描述，其类似对于工作对象的描述，相比于C++语言。时序所处理的，是其过程中的每一段进程的判断；控制所处理的，是其对结果和开始的判断。两种状态机所处理的机制不同。

而一般对于时序的描述用Moore状态机，其输出仅与当前状态有关，类似时钟的信号产生仅与当前的所处的状态；而对于控制的描述用mealy状态机。其输出不仅与当前输入有关还与当前状态有关，类似其控制输出的信号。

-For FPGA state machine design experience

For FPGA state machine design is divided into two categories, divided output mealy state machine and Moore state machine, mealy state machine has not only the current state of the input current, whereas the output Moore state machine only with the current status. For the descr iption of the state machine must first know the input, output, current state, the basic definition of a state.

For non-state machine design, the first to have an initial state, generically named IDLE, its status is generally set at the time of the reset signal comes.

Sensitive to the clock signal at its clock period as a maximum of the total circulating state, a clock signal under the most state instruction, a timing chart for describing general　for non-sensitive clock signal, for each current working Analyzing the state, generally used to describe control. For the descr iption of the timing diagram, which is similar to the control process, as compared to the C language