model/mt46v4m16.vhd
model/mti_pkg.vhd
route/ddr_sdram.csf
route/ddr_sdram.esf
route/ddr_sdram.psf
route/ddr_sdram.quartus
route/ddr_sdram.vqm
route/pll1.vhd
simulation/APEX20KE_MF.VHD
simulation/ddr_sdram_tb.vhd
simulation/modelsim.ini
simulation/mti_pkg.bak
simulation/readme.txt
simulation/wave.do
simulation/work/altcam/behave.psm
simulation/work/altclklock/behavior.dat
simulation/work/altclklock/behavior.psm
simulation/work/altlvds_rx/behavior.psm
simulation/work/altlvds_tx/behavior.psm
simulation/work/control_interface/rtl.dat
simulation/work/control_interface/rtl.psm
simulation/work/ddr_command/rtl.dat
simulation/work/ddr_command/rtl.psm
simulation/work/ddr_command/_primary.dat
simulation/work/ddr_control_interface/rtl.dat
simulation/work/ddr_control_interface/rtl.psm
simulation/work/ddr_control_interface/_primary.dat
simulation/work/ddr_data_path/rtl.dat
simulation/work/ddr_data_path/rtl.psm
simulation/work/ddr_data_path/_primary.dat
simulation/work/ddr_sdram/rtl.dat
simulation/work/ddr_sdram/rtl.psm
simulation/work/ddr_sdram/_primary.dat
simulation/work/ddr_sdram_tb/rtl.dat
simulation/work/ddr_sdram_tb/rtl.psm
simulation/work/io_utils/body.psm
simulation/work/lpm_components/body.dat
simulation/work/lpm_components/body.psm
simulation/work/lpm_components/_primary.dat
simulation/work/lpm_components/_vhdl.psm
simulation/work/mt46v4m16/behave.dat
simulation/work/mt46v4m16/behave.psm
simulation/work/mt46v4m16/_primary.dat
simulation/work/mti_pkg/body.dat
simulation/work/mti_pkg/body.psm
simulation/work/mti_pkg/_primary.dat
simulation/work/mti_pkg/_vhdl.psm
simulation/work/pll1/syn.dat
simulation/work/pll1/syn.psm
simulation/work/pll1/_primary.dat
simulation/work/std_logic_arith/body.psm
simulation/work/_info
source/ddr_command.vhd
source/ddr_control_interface.vhd
source/ddr_data_path.vhd
source/ddr_sdram.vhd
synthesis/synplicity/ddr_sdram.prj
synthesis/synplicity/rev_1/ddr_sdram.srm
synthesis/synplicity/rev_1/ddr_sdram.srr
synthesis/synplicity/rev_1/ddr_sdram.srs
synthesis/synplicity/rev_1/ddr_sdram.tcl
synthesis/synplicity/rev_1/ddr_sdram.tlg
synthesis/synplicity/rev_1/ddr_sdram.vqm
synthesis/synplicity/rev_1/ddr_sdram.xrf
synthesis/synplicity/rev_1/ddr_sdram_rm.tcl
readme.txt
simulation/work/altcam
simulation/work/altclklock
simulation/work/altlvds_rx
simulation/work/altlvds_tx
simulation/work/control_interface
simulation/work/ddr_command
simulation/work/ddr_control_interface
simulation/work/ddr_data_path
simulation/work/ddr_sdram
simulation/work/ddr_sdram_tb
simulation/work/io_utils
simulation/work/lpm_components
simulation/work/mt46v4m16
simulation/work/mti_pkg
simulation/work/pll1
simulation/work/std_logic_arith
synthesis/synplicity/rev_1
simulation/work
synthesis/synplicity
model
route
simulation
source
synthesis