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文件名称:MEM

  • 所属分类：
    Communication
  • 标签属性：
    [ASM] [源码]
  • 上传时间：
    2016-10-07
  • 文件大小：
    557.66kb
  • 已下载：
    0次
  • 提 供 者：
    go***
  • 相关连接：
    无
  • 下载说明：
    别用迅雷下载，失败请重下，重下不扣分！
修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

hereby i have attached memory controller vip by using system verilog hope this will be helpfule for u
(系统自动生成,下载前可以参看下载内容)

下载文件列表

MEM/design/rtl/CVS/Entries
MEM/design/rtl/CVS/Repository
MEM/design/rtl/CVS/Root
MEM/design/rtl/verilog/.mc_adr_sel.v.swo
MEM/design/rtl/verilog/.mc_top.v.swn
MEM/design/rtl/verilog/CVS/Entries
MEM/design/rtl/verilog/CVS/Repository
MEM/design/rtl/verilog/CVS/Root
MEM/design/rtl/verilog/mc_adr_sel.v
MEM/design/rtl/verilog/mc_cs_rf.v
MEM/design/rtl/verilog/mc_defines.v
MEM/design/rtl/verilog/mc_dp.v
MEM/design/rtl/verilog/mc_incn_r.v
MEM/design/rtl/verilog/mc_mem_if.v
MEM/design/rtl/verilog/mc_obct.v
MEM/design/rtl/verilog/mc_obct_top.v
MEM/design/rtl/verilog/mc_rd_fifo.v
MEM/design/rtl/verilog/mc_refresh.v
MEM/design/rtl/verilog/mc_rf.v
MEM/design/rtl/verilog/mc_timing.v
MEM/design/rtl/verilog/mc_top.v
MEM/design/rtl/verilog/mc_wb_if.v
MEM/design/rtl/verilog/timescale.v
MEM/mc/mem_intf.sv
MEM/mc/mem_intf.sv~
MEM/mc/readme.txt
MEM/MemoryModels/160b3ver/adv_bb.v
MEM/MemoryModels/160b3ver/dp160b3b.v
MEM/MemoryModels/160b3ver/DP160B3B_RU.V
MEM/MemoryModels/160b3ver/dp160b3t.v
MEM/MemoryModels/160b3ver/f160b3b.bkb
MEM/MemoryModels/160b3ver/f160b3b.bke
MEM/MemoryModels/160b3ver/f160b3b.bkt
MEM/MemoryModels/160b3ver/f160b3t.bkb
MEM/MemoryModels/160b3ver/f160b3t.bke
MEM/MemoryModels/160b3ver/f160b3t.bkt
MEM/MemoryModels/160b3ver/read.me
MEM/MemoryModels/160b3ver/t160b3b.v
MEM/MemoryModels/160b3ver/t160b3t.v
MEM/MemoryModels/sdram_models/16Mx16/mt48lc16m16a2.v
MEM/MemoryModels/sdram_models/16Mx8/mt48lc16m8a2.v
MEM/MemoryModels/sdram_models/2Mx32/bank0.txt
MEM/MemoryModels/sdram_models/2Mx32/bank1.txt
MEM/MemoryModels/sdram_models/2Mx32/bank2.txt
MEM/MemoryModels/sdram_models/2Mx32/bank3.txt
MEM/MemoryModels/sdram_models/2Mx32/mt48lc2m32b2.v
MEM/MemoryModels/sdram_models/32Mx8/mt48lc32m8a2.v
MEM/MemoryModels/sdram_models/4Mx16/bank0.txt
MEM/MemoryModels/sdram_models/4Mx16/bank1.txt
MEM/MemoryModels/sdram_models/4Mx16/bank2.txt
MEM/MemoryModels/sdram_models/4Mx16/bank3.txt
MEM/MemoryModels/sdram_models/4Mx16/mt48lc4m16a2.v
MEM/MemoryModels/sdram_models/4Mx32/mt48lc4m32b2.v
MEM/MemoryModels/sdram_models/8Mx16/mt48lc8m16a2.v
MEM/MemoryModels/sdram_models/8Mx8/bank0.txt
MEM/MemoryModels/sdram_models/8Mx8/bank1.txt
MEM/MemoryModels/sdram_models/8Mx8/bank2.txt
MEM/MemoryModels/sdram_models/8Mx8/bank3.txt
MEM/MemoryModels/sdram_models/8Mx8/mt48lc8m8a2.v
MEM/MemoryModels/sram_models/IDT71T67802/idt71t67802s133.v
MEM/MemoryModels/sram_models/IDT71T67802/idt71t67802s150.v
MEM/MemoryModels/sram_models/IDT71T67802/idt71t67802s166.v
MEM/MemoryModels/sram_models/IDT71T67802/idt_512Kx18_PBSRAM_test.v
MEM/MemoryModels/sram_models/IDT71T67802/readme_71T67802
MEM/MemoryModels/sram_models/MicronSRAM/mt58l1my18d.v
MEM/MemoryModels/SyncCS/.sync_cs_dev.v.swo
MEM/MemoryModels/SyncCS/sync_cs_dev.v
MEM/top/modelsim.ini
MEM/top/run.do
MEM/top/run2.do
MEM/top/run2.do~
MEM/top/topsvh.svh
MEM/top/topsvh.svh~
MEM/top/vsim.wlf
MEM/top/wb_top.sv
MEM/top/wb_top.sv~
MEM/top/work/@intel@adv@boot/_primary.dat
MEM/top/work/@intel@adv@boot/_primary.dbs
MEM/top/work/@intel@adv@boot/_primary.vhd
MEM/top/work/mc_adr_sel/verilog.asm
MEM/top/work/mc_adr_sel/verilog.rw
MEM/top/work/mc_adr_sel/_primary.dat
MEM/top/work/mc_adr_sel/_primary.dbs
MEM/top/work/mc_adr_sel/_primary.vhd
MEM/top/work/mc_cs_rf/verilog.asm
MEM/top/work/mc_cs_rf/verilog.rw
MEM/top/work/mc_cs_rf/_primary.dat
MEM/top/work/mc_cs_rf/_primary.dbs
MEM/top/work/mc_cs_rf/_primary.vhd
MEM/top/work/mc_cs_rf_dummy/_primary.dat
MEM/top/work/mc_cs_rf_dummy/_primary.dbs
MEM/top/work/mc_cs_rf_dummy/_primary.vhd
MEM/top/work/mc_dp/verilog.asm
MEM/top/work/mc_dp/verilog.rw
MEM/top/work/mc_dp/_primary.dat
MEM/top/work/mc_dp/_primary.dbs
MEM/top/work/mc_dp/_primary.vhd
MEM/top/work/mc_incn_r/verilog.asm
MEM/top/work/mc_incn_r/verilog.rw
MEM/top/work/mc_incn_r/_primary.dat
MEM/top/work/mc_incn_r/_primary.dbs
MEM/top/work/mc_incn_r/_primary.vhd
MEM/top/work/mc_mem_if/verilog.asm
MEM/top/work/mc_mem_if/verilog.rw
MEM/top/work/mc_mem_if/_primary.dat
MEM/top/work/mc_mem_if/_primary.dbs
MEM/top/work/mc_mem_if/_primary.vhd
MEM/top/work/mc_obct/verilog.asm
MEM/top/work/mc_obct/verilog.rw
MEM/top/work/mc_obct/_primary.dat
MEM/top/work/mc_obct/_primary.dbs
MEM/top/work/mc_obct/_primary.vhd
MEM/top/work/mc_obct_dummy/_primary.dat
MEM/top/work/mc_obct_dummy/_primary.dbs
MEM/top/work/mc_obct_dummy/_primary.vhd
MEM/top/work/mc_obct_top/verilog.asm
MEM/top/work/mc_obct_top/verilog.rw
MEM/top/work/mc_obct_top/_primary.dat
MEM/top/work/mc_obct_top/_primary.dbs
MEM/top/work/mc_obct_top/_primary.vhd
MEM/top/work/mc_rd_fifo/verilog.asm
MEM/top/work/mc_rd_fifo/verilog.rw
MEM/top/work/mc_rd_fifo/_primary.dat
MEM/top/work/mc_rd_fifo/_primary.dbs
MEM/top/work/mc_rd_fifo/_primary.vhd
MEM/top/work/mc_refresh/verilog.asm
MEM/top/work/mc_refresh/verilog.rw
MEM/top/work/mc_refresh/_primary.dat
MEM/top/work/mc_refresh/_primary.dbs
MEM/top/work/mc_refresh/_primary.vhd
MEM/top/work/mc_rf/verilog.asm
MEM/top/work/mc_rf/verilog.rw
MEM/top/work/mc_rf/_primary.dat
MEM/top/work/mc_rf/_primary.dbs
MEM/top/work/mc_rf/_primary.vhd
MEM/top/work/mc_timing/verilog.asm
MEM/top/work/mc_timing/verilog.rw
MEM/top/work/mc_timing/_primary.dat
MEM/top/work/mc_timing/_primary.

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