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文件名称:uart

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  • 上传时间:
    2016-10-31
  • 文件大小:
    6.61mb
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    0次
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    别用迅雷下载,失败请重下,重下不扣分!

介绍说明--下载内容来自于网络,使用问题请自行百度

uart串口通信协议 可以在modelsim里进行仿真验证- uart can be simulation in modelsim
(系统自动生成,下载前可以参看下载内容)

下载文件列表

uart/
uart/clk_div.v
uart/clk_div.v.bak
uart/clk_div.vwf
uart/db/
uart/db/logic_util_heursitic.dat
uart/db/prev_cmp_uart_top.qmsg
uart/db/uart_top.(0).cnf.cdb
uart/db/uart_top.(0).cnf.hdb
uart/db/uart_top.(1).cnf.cdb
uart/db/uart_top.(1).cnf.hdb
uart/db/uart_top.(2).cnf.cdb
uart/db/uart_top.(2).cnf.hdb
uart/db/uart_top.(3).cnf.cdb
uart/db/uart_top.(3).cnf.hdb
uart/db/uart_top.ae.hdb
uart/db/uart_top.asm.qmsg
uart/db/uart_top.asm.rdb
uart/db/uart_top.asm_labs.ddb
uart/db/uart_top.cbx.xml
uart/db/uart_top.cmp.bpm
uart/db/uart_top.cmp.cdb
uart/db/uart_top.cmp.hdb
uart/db/uart_top.cmp.idb
uart/db/uart_top.cmp.kpt
uart/db/uart_top.cmp.logdb
uart/db/uart_top.cmp.rdb
uart/db/uart_top.cmp_merge.kpt
uart/db/uart_top.cycloneive_io_sim_cache.45um_ff_1200mv_0c_fast.hsd
uart/db/uart_top.cycloneive_io_sim_cache.45um_tt_1200mv_0c_slow.hsd
uart/db/uart_top.cycloneive_io_sim_cache.45um_tt_1200mv_85c_slow.hsd
uart/db/uart_top.db_info
uart/db/uart_top.eda.qmsg
uart/db/uart_top.fit.qmsg
uart/db/uart_top.hier_info
uart/db/uart_top.hif
uart/db/uart_top.ipinfo
uart/db/uart_top.lpc.html
uart/db/uart_top.lpc.rdb
uart/db/uart_top.lpc.txt
uart/db/uart_top.map.ammdb
uart/db/uart_top.map.bpm
uart/db/uart_top.map.cdb
uart/db/uart_top.map.hdb
uart/db/uart_top.map.kpt
uart/db/uart_top.map.logdb
uart/db/uart_top.map.qmsg
uart/db/uart_top.map.rdb
uart/db/uart_top.map_bb.cdb
uart/db/uart_top.map_bb.hdb
uart/db/uart_top.map_bb.logdb
uart/db/uart_top.pre_map.cdb
uart/db/uart_top.pre_map.hdb
uart/db/uart_top.pti_db_list.ddb
uart/db/uart_top.root_partition.map.reg_db.cdb
uart/db/uart_top.routing.rdb
uart/db/uart_top.rpp.qmsg
uart/db/uart_top.rtlv.hdb
uart/db/uart_top.rtlv_sg.cdb
uart/db/uart_top.rtlv_sg_swap.cdb
uart/db/uart_top.sgate.rvd
uart/db/uart_top.sgate_sm.rvd
uart/db/uart_top.sgdiff.cdb
uart/db/uart_top.sgdiff.hdb
uart/db/uart_top.sld_design_entry.sci
uart/db/uart_top.sld_design_entry_dsc.sci
uart/db/uart_top.smart_action.txt
uart/db/uart_top.smp_dump.txt
uart/db/uart_top.sta.qmsg
uart/db/uart_top.sta.rdb
uart/db/uart_top.sta_cmp.6_slow_1200mv_85c.tdb
uart/db/uart_top.stingray_io_sim_cache.99um_ff_1200mv_0c_fast.hsd
uart/db/uart_top.stingray_io_sim_cache.99um_tt_1200mv_0c_slow.hsd
uart/db/uart_top.stingray_io_sim_cache.99um_tt_1200mv_85c_slow.hsd
uart/db/uart_top.syn_hier_info
uart/db/uart_top.tis_db_list.ddb
uart/db/uart_top.tiscmp.fast_1200mv_0c.ddb
uart/db/uart_top.tiscmp.slow_1200mv_0c.ddb
uart/db/uart_top.tiscmp.slow_1200mv_85c.ddb
uart/db/uart_top.vpr.ammdb
uart/incremental_db/
uart/incremental_db/README
uart/incremental_db/compiled_partitions/
uart/incremental_db/compiled_partitions/uart_top.db_info
uart/incremental_db/compiled_partitions/uart_top.root_partition.cmp.ammdb
uart/incremental_db/compiled_partitions/uart_top.root_partition.cmp.cdb
uart/incremental_db/compiled_partitions/uart_top.root_partition.cmp.dfp
uart/incremental_db/compiled_partitions/uart_top.root_partition.cmp.hdb
uart/incremental_db/compiled_partitions/uart_top.root_partition.cmp.kpt
uart/incremental_db/compiled_partitions/uart_top.root_partition.cmp.logdb
uart/incremental_db/compiled_partitions/uart_top.root_partition.cmp.rcfdb
uart/incremental_db/compiled_partitions/uart_top.root_partition.map.cdb
uart/incremental_db/compiled_partitions/uart_top.root_partition.map.dpi
uart/incremental_db/compiled_partitions/uart_top.root_partition.map.hbdb.cdb
uart/incremental_db/compiled_partitions/uart_top.root_partition.map.hbdb.hb_info
uart/incremental_db/compiled_partitions/uart_top.root_partition.map.hbdb.hdb
uart/incremental_db/compiled_partitions/uart_top.root_partition.map.hbdb.sig
uart/incremental_db/compiled_partitions/uart_top.root_partition.map.hdb
uart/incremental_db/compiled_partitions/uart_top.root_partition.map.kpt
uart/output_files/
uart/output_files/uart_top.asm.rpt
uart/output_files/uart_top.done
uart/output_files/uart_top.eda.rpt
uart/output_files/uart_top.fit.rpt
uart/output_files/uart_top.fit.smsg
uart/output_files/uart_top.fit.summary
uart/output_files/uart_top.flow.rpt
uart/output_files/uart_top.jdi
uart/output_files/uart_top.map.rpt
uart/output_files/uart_top.map.smsg
uart/output_files/uart_top.map.summary
uart/output_files/uart_top.pin
uart/output_files/uart_top.sof
uart/output_files/uart_top.sta.rpt
uart/output_files/uart_top.sta.summary
uart/simulation/
uart/simulation/modelsim/
uart/simulation/modelsim/uart_top.sft
uart/simulation/modelsim/uart_top.vo
uart/simulation/modelsim/uart_top_modelsim.xrf
uart/simulation/qsim/
uart/simulation/qsim/transcript
uart/simulation/qsim/uart_top.do
uart/simulation/qsim/uart_top.msim.vcd
uart/simulation/qsim/uart_top.msim.vwf
uart/simulation/qsim/uart_top.sim.vwf
uart/simulation/qsim/uart_top.vo
uart/simulation/qsim/uart_top.vt
uart/simulation/qsim/vsim.wlf
uart/simulation/qsim/work/
uart/simulation/qsim/work/_info
uart/simulation/qsim/work/_temp/
uart/simulation/qsim/work/_vmake
uart/simulation/qsim/work/clk_div/
uart/simulation/qsim/work/clk_div/_primary.dat
uart/simulation/qsim/work/clk_div/_primary.dbs
uart/simulation/qsim/work/clk_div/_primary.vhd
uart/simulation/qsim/work/clk_div/verilog.prw
uart/simulation/qsim/work/clk_d

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