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文件名称:OExp11-OwnMCPU

  • 所属分类：
    VHDL-FPGA-Verilog
  • 标签属性：
    [PDF]
  • 上传时间：
    2016-11-02
  • 文件大小：
    7.17mb
  • 已下载：
    1次
  • 提 供 者：
    林***
  • 相关连接：
    无
  • 下载说明：
    别用迅雷下载，失败请重下，重下不扣分！
修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

浙江大学计算机组成实验课工程代码，多周期CPU设计控制器实现。-Multi-cycle CPU design of the controller.
(系统自动生成,下载前可以参看下载内容)

下载文件列表

OExp11-OwnMCPU/
OExp11-OwnMCPU/clk_div.sym
OExp11-OwnMCPU/code/
OExp11-OwnMCPU/code/clk_div.v
OExp11-OwnMCPU/code/Counter_3_IO.v
OExp11-OwnMCPU/code/ctrl.v
OExp11-OwnMCPU/code/Ext_32.v
OExp11-OwnMCPU/code/MIO_BUS_IO.v
OExp11-OwnMCPU/code/Multi_8CH32_IO.v
OExp11-OwnMCPU/code/MUX2T1_32.v
OExp11-OwnMCPU/code/MUX4T1_32.v
OExp11-OwnMCPU/code/MUX4T1_5.v
OExp11-OwnMCPU/code/M_datapath.v
OExp11-OwnMCPU/code/OExp_ALU.v
OExp11-OwnMCPU/code/PIO_IO.v
OExp11-OwnMCPU/code/REG32.v
OExp11-OwnMCPU/code/Regs.v
OExp11-OwnMCPU/code/SAnti_jitter_IO.v
OExp11-OwnMCPU/code/Seg7_Dev_IO.v
OExp11-OwnMCPU/code/SEnter_2_32_IO.v
OExp11-OwnMCPU/code/SPIO_IO.v
OExp11-OwnMCPU/code/SSeg7_Dev_IO.v
OExp11-OwnMCPU/Counter_x.ngc
OExp11-OwnMCPU/Counter_x.sym
OExp11-OwnMCPU/ctrl.ngc
OExp11-OwnMCPU/ctrl.sym
OExp11-OwnMCPU/Ext_32.sym
OExp11-OwnMCPU/ipcore_dir/
OExp11-OwnMCPU/ipcore_dir/coregen.cgp
OExp11-OwnMCPU/ipcore_dir/coregen.log
OExp11-OwnMCPU/ipcore_dir/create_RAM_B.tcl
OExp11-OwnMCPU/ipcore_dir/RAM_B/
OExp11-OwnMCPU/ipcore_dir/RAM_B.asy
OExp11-OwnMCPU/ipcore_dir/RAM_B.gise
OExp11-OwnMCPU/ipcore_dir/RAM_B.mif
OExp11-OwnMCPU/ipcore_dir/RAM_B.ncf
OExp11-OwnMCPU/ipcore_dir/RAM_B.ngc
OExp11-OwnMCPU/ipcore_dir/RAM_B.sym
OExp11-OwnMCPU/ipcore_dir/RAM_B.v
OExp11-OwnMCPU/ipcore_dir/RAM_B.veo
OExp11-OwnMCPU/ipcore_dir/RAM_B.xco
OExp11-OwnMCPU/ipcore_dir/RAM_B.xise
OExp11-OwnMCPU/ipcore_dir/RAM_B/blk_mem_gen_v7_3_readme.txt
OExp11-OwnMCPU/ipcore_dir/RAM_B/doc/
OExp11-OwnMCPU/ipcore_dir/RAM_B/doc/blk_mem_gen_v7_3_vinfo.html
OExp11-OwnMCPU/ipcore_dir/RAM_B/doc/pg058-blk-mem-gen.pdf
OExp11-OwnMCPU/ipcore_dir/RAM_B/example_design/
OExp11-OwnMCPU/ipcore_dir/RAM_B/example_design/RAM_B_exdes.ucf
OExp11-OwnMCPU/ipcore_dir/RAM_B/example_design/RAM_B_exdes.vhd
OExp11-OwnMCPU/ipcore_dir/RAM_B/example_design/RAM_B_exdes.xdc
OExp11-OwnMCPU/ipcore_dir/RAM_B/example_design/RAM_B_prod.vhd
OExp11-OwnMCPU/ipcore_dir/RAM_B/implement/
OExp11-OwnMCPU/ipcore_dir/RAM_B/implement/implement.bat
OExp11-OwnMCPU/ipcore_dir/RAM_B/implement/implement.sh
OExp11-OwnMCPU/ipcore_dir/RAM_B/implement/planAhead_ise.bat
OExp11-OwnMCPU/ipcore_dir/RAM_B/implement/planAhead_ise.sh
OExp11-OwnMCPU/ipcore_dir/RAM_B/implement/planAhead_ise.tcl
OExp11-OwnMCPU/ipcore_dir/RAM_B/implement/xst.prj
OExp11-OwnMCPU/ipcore_dir/RAM_B/implement/xst.scr
OExp11-OwnMCPU/ipcore_dir/RAM_B/simulation/
OExp11-OwnMCPU/ipcore_dir/RAM_B/simulation/addr_gen.vhd
OExp11-OwnMCPU/ipcore_dir/RAM_B/simulation/bmg_stim_gen.vhd
OExp11-OwnMCPU/ipcore_dir/RAM_B/simulation/bmg_tb_pkg.vhd
OExp11-OwnMCPU/ipcore_dir/RAM_B/simulation/checker.vhd
OExp11-OwnMCPU/ipcore_dir/RAM_B/simulation/data_gen.vhd
OExp11-OwnMCPU/ipcore_dir/RAM_B/simulation/functional/
OExp11-OwnMCPU/ipcore_dir/RAM_B/simulation/functional/simcmds.tcl
OExp11-OwnMCPU/ipcore_dir/RAM_B/simulation/functional/simulate_isim.bat
OExp11-OwnMCPU/ipcore_dir/RAM_B/simulation/functional/simulate_mti.bat
OExp11-OwnMCPU/ipcore_dir/RAM_B/simulation/functional/simulate_mti.do
OExp11-OwnMCPU/ipcore_dir/RAM_B/simulation/functional/simulate_mti.sh
OExp11-OwnMCPU/ipcore_dir/RAM_B/simulation/functional/simulate_ncsim.sh
OExp11-OwnMCPU/ipcore_dir/RAM_B/simulation/functional/simulate_vcs.sh
OExp11-OwnMCPU/ipcore_dir/RAM_B/simulation/functional/ucli_commands.key
OExp11-OwnMCPU/ipcore_dir/RAM_B/simulation/functional/vcs_session.tcl
OExp11-OwnMCPU/ipcore_dir/RAM_B/simulation/functional/wave_mti.do
OExp11-OwnMCPU/ipcore_dir/RAM_B/simulation/functional/wave_ncsim.sv
OExp11-OwnMCPU/ipcore_dir/RAM_B/simulation/RAM_B_synth.vhd
OExp11-OwnMCPU/ipcore_dir/RAM_B/simulation/RAM_B_tb.vhd
OExp11-OwnMCPU/ipcore_dir/RAM_B/simulation/random.vhd
OExp11-OwnMCPU/ipcore_dir/RAM_B/simulation/timing/
OExp11-OwnMCPU/ipcore_dir/RAM_B/simulation/timing/simcmds.tcl
OExp11-OwnMCPU/ipcore_dir/RAM_B/simulation/timing/simulate_isim.bat
OExp11-OwnMCPU/ipcore_dir/RAM_B/simulation/timing/simulate_mti.bat
OExp11-OwnMCPU/ipcore_dir/RAM_B/simulation/timing/simulate_mti.do
OExp11-OwnMCPU/ipcore_dir/RAM_B/simulation/timing/simulate_mti.sh
OExp11-OwnMCPU/ipcore_dir/RAM_B/simulation/timing/simulate_ncsim.sh
OExp11-OwnMCPU/ipcore_dir/RAM_B/simulation/timing/simulate_vcs.sh
OExp11-OwnMCPU/ipcore_dir/RAM_B/simulation/timing/ucli_commands.key
OExp11-OwnMCPU/ipcore_dir/RAM_B/simulation/timing/vcs_session.tcl
OExp11-OwnMCPU/ipcore_dir/RAM_B/simulation/timing/wave_mti.do
OExp11-OwnMCPU/ipcore_dir/RAM_B/simulation/timing/wave_ncsim.sv
OExp11-OwnMCPU/ipcore_dir/RAM_B_flist.txt
OExp11-OwnMCPU/ipcore_dir/RAM_B_xmdf.tcl
OExp11-OwnMCPU/ipcore_dir/summary.log
OExp11-OwnMCPU/ipcore_dir/tmp/
OExp11-OwnMCPU/ipcore_dir/tmp/RAM_B.lso
OExp11-OwnMCPU/ipcore_dir/tmp/_cg/
OExp11-OwnMCPU/ipcore_dir/tmp/_xmsgs/
OExp11-OwnMCPU/ipcore_dir/tmp/_xmsgs/pn_parser.xmsgs
OExp11-OwnMCPU/ipcore_dir/tmp/_xmsgs/xst.xmsgs
OExp11-OwnMCPU/ipcore_dir/xlnx_auto_0_xdb/
OExp11-OwnMCPU/ipcore_dir/_xmsgs/
OExp11-OwnMCPU/ipcore_dir/_xmsgs/cg.xmsgs
OExp11-OwnMCPU/ipcore_dir/_xmsgs/pn_parser.xmsgs
OExp11-OwnMCPU/iseconfig/
OExp11-OwnMCPU/iseconfig/M_datapath.xreport
OExp11-OwnMCPU/iseconfig/OExp11-OwnMCPU.projectmgr
OExp11-OwnMCPU/iseconfig/SOCMF.xreport
OExp11-OwnMCPU/MIO_BUS.ngc
OExp11-OwnMC

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