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文件名称:15_IP_core

  • 所属分类：
    VHDL-FPGA-Verilog
  • 标签属性：
    [PDF]
  • 上传时间：
    2016-11-11
  • 文件大小：
    2.33mb
  • 已下载：
    0次
  • 提 供 者：
    To***
  • 相关连接：
    无
  • 下载说明：
    别用迅雷下载，失败请重下，重下不扣分！
修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

ata, 3des vgs等ip核。 ECE395 GPU:

-ata, 3des vgs and other ip core. ECE395 GPU:
(系统自动生成,下载前可以参看下载内容)

下载文件列表

395_vgs.tar.gz
ata.tar.gz
ata/ata/bench/CVS/Entries
ata/ata/bench/CVS/Repository
ata/ata/bench/CVS/Root
ata/ata/bench/verilog/ata_device.v
ata/ata/bench/verilog/CVS/Entries
ata/ata/bench/verilog/CVS/Repository
ata/ata/bench/verilog/CVS/Root
ata/ata/bench/verilog/tests.v
ata/ata/bench/verilog/test_bench_top.v
ata/ata/bench/verilog/wb_mast_model.v
ata/ata/bench/verilog/wb_model_defines.v
ata/ata/bench/verilog/wb_slv_model.v
ata/ata/bench/vhdl/CVS/Entries
ata/ata/bench/vhdl/CVS/Repository
ata/ata/bench/vhdl/CVS/Root
ata/ata/CVS/Entries
ata/ata/CVS/Repository
ata/ata/CVS/Root
ata/ata/doc/CVS/Entries
ata/ata/doc/CVS/Repository
ata/ata/doc/CVS/Root
ata/ata/doc/preliminary_ata_core.pdf
ata/ata/doc/src/ata_core.doc
ata/ata/doc/src/CVS/Entries
ata/ata/doc/src/CVS/Repository
ata/ata/doc/src/CVS/Root
ata/ata/documentation/CVS/Entries
ata/ata/documentation/CVS/Repository
ata/ata/documentation/CVS/Root
ata/ata/rtl/CVS/Entries
ata/ata/rtl/CVS/Repository
ata/ata/rtl/CVS/Root
ata/ata/rtl/verilog/CVS/Entries
ata/ata/rtl/verilog/CVS/Repository
ata/ata/rtl/verilog/CVS/Root
ata/ata/rtl/verilog/ocidec-1/atahost_controller.v
ata/ata/rtl/verilog/ocidec-1/atahost_pio_tctrl.v
ata/ata/rtl/verilog/ocidec-1/atahost_top.v
ata/ata/rtl/verilog/ocidec-1/atahost_wb_slave.v
ata/ata/rtl/verilog/ocidec-1/CVS/Entries
ata/ata/rtl/verilog/ocidec-1/CVS/Repository
ata/ata/rtl/verilog/ocidec-1/CVS/Root
ata/ata/rtl/verilog/ocidec-1/revision_history.txt
ata/ata/rtl/verilog/ocidec-1/ro_cnt.v
ata/ata/rtl/verilog/ocidec-1/timescale.v
ata/ata/rtl/verilog/ocidec-1/ud_cnt.v
ata/ata/rtl/verilog/ocidec-2/atahost_controller.v
ata/ata/rtl/verilog/ocidec-2/atahost_pio_actrl.v
ata/ata/rtl/verilog/ocidec-2/atahost_pio_tctrl.v
ata/ata/rtl/verilog/ocidec-2/atahost_top.v
ata/ata/rtl/verilog/ocidec-2/atahost_wb_slave.v
ata/ata/rtl/verilog/ocidec-2/CVS/Entries
ata/ata/rtl/verilog/ocidec-2/CVS/Repository
ata/ata/rtl/verilog/ocidec-2/CVS/Root
ata/ata/rtl/verilog/ocidec-2/revision_history.txt
ata/ata/rtl/verilog/ocidec-2/ro_cnt.v
ata/ata/rtl/verilog/ocidec-2/timescale.v
ata/ata/rtl/verilog/ocidec-2/ud_cnt.v
ata/ata/rtl/vhdl/CVS/Entries
ata/ata/rtl/vhdl/CVS/Repository
ata/ata/rtl/vhdl/CVS/Root
ata/ata/rtl/vhdl/ocidec1/atahost_controller.vhd
ata/ata/rtl/vhdl/ocidec1/atahost_pio_tctrl.vhd
ata/ata/rtl/vhdl/ocidec1/atahost_top.vhd
ata/ata/rtl/vhdl/ocidec1/atahost_wb_slave.vhd
ata/ata/rtl/vhdl/ocidec1/CVS/Entries
ata/ata/rtl/vhdl/ocidec1/CVS/Repository
ata/ata/rtl/vhdl/ocidec1/CVS/Root
ata/ata/rtl/vhdl/ocidec1/revision_history.txt
ata/ata/rtl/vhdl/ocidec1/ro_cnt.vhd
ata/ata/rtl/vhdl/ocidec1/ud_cnt.vhd
ata/ata/rtl/vhdl/ocidec2/atahost_controller.vhd
ata/ata/rtl/vhdl/ocidec2/atahost_pio_actrl.vhd
ata/ata/rtl/vhdl/ocidec2/atahost_pio_tctrl.vhd
ata/ata/rtl/vhdl/ocidec2/atahost_top.vhd
ata/ata/rtl/vhdl/ocidec2/atahost_wb_slave.vhd
ata/ata/rtl/vhdl/ocidec2/CVS/Entries
ata/ata/rtl/vhdl/ocidec2/CVS/Repository
ata/ata/rtl/vhdl/ocidec2/CVS/Root
ata/ata/rtl/vhdl/ocidec2/revision_history.txt
ata/ata/rtl/vhdl/ocidec2/ro_cnt.vhd
ata/ata/rtl/vhdl/ocidec2/ud_cnt.vhd
ata/ata/rtl/vhdl/ocidec3/atahost_controller.vhd
ata/ata/rtl/vhdl/ocidec3/atahost_dma_actrl.vhd
ata/ata/rtl/vhdl/ocidec3/atahost_dma_tctrl.vhd
ata/ata/rtl/vhdl/ocidec3/atahost_fifo.vhd
ata/ata/rtl/vhdl/ocidec3/atahost_lfsr.vhd
ata/ata/rtl/vhdl/ocidec3/atahost_pio_actrl.vhd
ata/ata/rtl/vhdl/ocidec3/atahost_pio_controller.vhd
ata/ata/rtl/vhdl/ocidec3/atahost_pio_tctrl.vhd
ata/ata/rtl/vhdl/ocidec3/atahost_reg_buf.vhd
ata/ata/rtl/vhdl/ocidec3/atahost_top.vhd
ata/ata/rtl/vhdl/ocidec3/atahost_wb_slave.vhd
ata/ata/rtl/vhdl/ocidec3/CVS/Entries
ata/ata/rtl/vhdl/ocidec3/CVS/Repository
ata/ata/rtl/vhdl/ocidec3/CVS/Root
ata/ata/rtl/vhdl/ocidec3/revision_history.txt
ata/ata/rtl/vhdl/ocidec3/ro_cnt.vhd
ata/ata/rtl/vhdl/ocidec3/ud_cnt.vhd
ata/ata/sim/CVS/Entries
ata/ata/sim/CVS/Repository
ata/ata/sim/CVS/Root
ata/ata/sim/gate_sim/bin/CVS/Entries
ata/ata/sim/gate_sim/bin/CVS/Repository
ata/ata/sim/gate_sim/bin/CVS/Root
ata/ata/sim/gate_sim/CVS/Entries
ata/ata/sim/gate_sim/CVS/Repository
ata/ata/sim/gate_sim/CVS/Root
ata/ata/sim/gate_sim/run/CVS/Entries
ata/ata/sim/gate_sim/run/CVS/Repository
ata/ata/sim/gate_sim/run/CVS/Root
ata/ata/sim/rtl_sim/bin/CVS/Entries
ata/ata/sim/rtl_sim/bin/CVS/Repository
ata/ata/sim/rtl_sim/bin/CVS/Root
ata/ata/sim/rtl_sim/bin/Makefile
ata/ata/sim/rtl_sim/CVS/Entries
ata/ata/sim/rtl_sim/CVS/Repository
ata/ata/sim/rtl_sim/CVS/Root
ata/ata/sim/rtl_sim/run/CVS/Entries
ata/ata/sim/rtl_sim/run/CVS/Repository
ata/ata/sim/rtl_sim/run/CVS/Root
ata/ata/syn/bin/comp.dc
ata/ata/syn/bin/CVS/Entries
ata/ata/syn/bin/CVS/Repository
ata/ata/syn/bin/CVS/Root
ata/ata/syn/bin/design_spec.dc
ata/ata/syn/bin/lib_spec.dc
ata/ata/syn/bin/read.dc
ata/ata/syn/CVS/Entries
ata/ata/syn/CVS/Repository
ata/ata/syn/CVS/Root
ata/ata/syn/log/CVS/Entries
ata/ata/syn/log/CVS/Repository
ata/ata/syn/log/CVS/Root
ata/ata/syn/out/CVS/Entries
ata/ata/syn/out/CVS/Repository
ata/ata/syn/out/CVS/Root
ata/ata/syn/run/CVS/Entries
ata/ata/syn/run/CVS/Repository
ata/ata/syn/run/CVS/Root
ata/ata/verilog/CVS/Entries
ata/ata/verilog/CVS/Repository
ata/ata/verilog/CVS/Root
ata/ata/verilo

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