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文件名称:RD1213_Video_Pipeline

  • 所属分类：
    VHDL-FPGA-Verilog
  • 标签属性：
    [VHDL] [源码]
  • 上传时间：
    2016-11-26
  • 文件大小：
    6.44mb
  • 已下载：
    0次
  • 提 供 者：
    吴**
  • 相关连接：
    无
  • 下载说明：
    别用迅雷下载，失败请重下，重下不扣分！
修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

This document describes the structure and implementation of a video pipeline demo design running in the Lattice

ECP3-150EA-8FN1156C device based on the Sparrowhawk FX Board. This demo takes two of the four video

streams DVI and SDI inputs and then combines them into one with different configuration modes.-This document describes the structure and implementation of a video pipeline demo design running in the Lattice

ECP3-150EA-8FN1156C device based on the Sparrowhawk FX Board. This demo takes two of the four video

streams　DVI and SDI inputs and then combines them into one with different configuration modes.
(系统自动生成,下载前可以参看下载内容)

下载文件列表

video_pipeline.bit
par/
par/.floorplanner.ini
par/.run_manager.ini
par/.setting.ini
par/.spreadsheet_view.ini
par/.spread_sheet.ini
par/blk2_text_index.mem
par/blk3_text_index.mem
par/chip.v
par/menu.mem
par/osd_text.mem
par/pcs_hdmi_10b.txt
par/pcs_sdi.txt
par/prom_init.mem
par/reportview.xml
par/video_pipeline.ccl
par/video_pipeline.ldf
par/video_pipeline.lpf
par/video_pipeline.rva
par/video_pipeline.rvl
par/video_pipeline.rvs
par/video_pipeline.svf
par/video_pipeline.trc
par/video_pipeline.xcf
par/video_pipeline1.sty
par/video_pipeline_tcl.html
par/video_pipeline_video_pipeline.hub
source/
source/blk2_text_index.mem
source/blk3_text_index.mem
source/data_switch_diff_clk.v
source/ddr3_sdram_mem_top.v
source/dout_sdi_and_hdmi.v
source/framer.v
source/hdmi_rec_to_dsp.v
source/hdmi_rx_tx.v
source/hdmi_tx_color_bar.v
source/hdmi_tx_sync_1080p.v
source/ip/
source/ip/csc/
source/ip/csc/pmi_dsp_multoppeEoo1910pA182cfef2e1.ngo
source/ip/csc/pmi_dsp_multoppeEoo1910pA182cfef2e1_0.ngo
source/ip/csc/pmi_dsp_multoppeEoo1910pA182cfef2e1_1.ngo
source/ip/csc/pmi_dsp_multoppeEoo1910pA182cfef2e1_2.ngo
source/ip/csc/pmi_dsp_multoppeEoo1910pA182cfef2e1_3.ngo
source/ip/csc/pmi_dsp_multoppeEoo198pA182ced1e84.ngo
source/ip/csc/pmi_dsp_multoppeEoo198pA182ced1e84_0.ngo
source/ip/csc/pmi_dsp_multoppeEoo198pA182ced1e84_1.ngo
source/ip/csc/pmi_dsp_multoppeEoo198pA182ced1e84_2.ngo
source/ip/csc/pmi_dsp_multoppeEoo198pA182ced1e84_3.ngo
source/ip/csc/pmi_dsp_multoppeEoo198pA182ced1e84_4.ngo
source/ip/csc/pmi_dsp_multoppeEoo198pA182ced1e84_5.ngo
source/ip/csc/pmi_dsp_multoppeEoo198pA182ced1e84_6.ngo
source/ip/csc/pmi_dsp_multoppeEoo198pA182ced1e84_7.ngo
source/ip/csc/rgb_to_ycbcr.ipx
source/ip/csc/rgb_to_ycbcr.lpc
source/ip/csc/rgb_to_ycbcr.ngo
source/ip/csc/rgb_to_ycbcr_bb.v
source/ip/csc/ycbcr_to_rgb.ipx
source/ip/csc/ycbcr_to_rgb.lpc
source/ip/csc/ycbcr_to_rgb.ngo
source/ip/csc/ycbcr_to_rgb_bb.v
source/ip/ddr3_32b_0/
source/ip/ddr3_32b_0/ddr3_32b_0.ipx
source/ip/ddr3_32b_0/ddr3_32b_0.lpc
source/ip/ddr3_32b_0/ddr3_32b_0.ngo
source/ip/ddr3_32b_0/ddr3_32b_0_bb.v
source/ip/ddr3_32b_0/ddr_p_eval/
source/ip/ddr3_32b_0/ddr_p_eval/ddr3_32b_0/
source/ip/ddr3_32b_0/ddr_p_eval/ddr3_32b_0/impl/
source/ip/ddr3_32b_0/ddr_p_eval/ddr3_32b_0/impl/ddr3_sdram_mem_top_wrapper.v
source/ip/ddr3_32b_0/ddr_p_eval/ddr3_32b_0/impl/precision/
source/ip/ddr3_32b_0/ddr_p_eval/ddr3_32b_0/impl/precision/ddr3_32b_0_eval.ldf
source/ip/ddr3_32b_0/ddr_p_eval/ddr3_32b_0/impl/precision/ddr3_32b_0_eval.lpf
source/ip/ddr3_32b_0/ddr_p_eval/ddr3_32b_0/impl/precision/ddr3_32b_0_eval.sty
source/ip/ddr3_32b_0/ddr_p_eval/ddr3_32b_0/impl/precision/post_route_trace.prf
source/ip/ddr3_32b_0/ddr_p_eval/ddr3_32b_0/impl/synplify/
source/ip/ddr3_32b_0/ddr_p_eval/ddr3_32b_0/impl/synplify/ddr3_32b_0_eval.ldf
source/ip/ddr3_32b_0/ddr_p_eval/ddr3_32b_0/impl/synplify/ddr3_32b_0_eval.lpf
source/ip/ddr3_32b_0/ddr_p_eval/ddr3_32b_0/impl/synplify/ddr3_32b_0_eval.sty
source/ip/ddr3_32b_0/ddr_p_eval/ddr3_32b_0/impl/synplify/post_route_trace.prf
source/ip/ddr3_32b_0/ddr_p_eval/ddr3_32b_0/sim/
source/ip/ddr3_32b_0/ddr_p_eval/ddr3_32b_0/sim/aldec/
source/ip/ddr3_32b_0/ddr_p_eval/ddr3_32b_0/sim/aldec/ddr3_32b_0_eval.do
source/ip/ddr3_32b_0/ddr_p_eval/ddr3_32b_0/sim/aldec/ddr3_32b_0_gatesim_precision.do
source/ip/ddr3_32b_0/ddr_p_eval/ddr3_32b_0/sim/aldec/ddr3_32b_0_gatesim_synplify.do
source/ip/ddr3_32b_0/ddr_p_eval/ddr3_32b_0/sim/modelsim/
source/ip/ddr3_32b_0/ddr_p_eval/ddr3_32b_0/sim/modelsim/ddr3_32b_0_eval.do
source/ip/ddr3_32b_0/ddr_p_eval/ddr3_32b_0/sim/modelsim/ddr3_32b_0_gatesim_precision.do
source/ip/ddr3_32b_0/ddr_p_eval/ddr3_32b_0/sim/modelsim/ddr3_32b_0_gatesim_synplify.do
source/ip/ddr3_32b_0/ddr_p_eval/ddr3_32b_0/sim/modelsim/wave.do
source/ip/ddr3_32b_0/ddr_p_eval/ddr3_32b_0/src/
source/ip/ddr3_32b_0/ddr_p_eval/ddr3_32b_0/src/params/
source/ip/ddr3_32b_0/ddr_p_eval/ddr3_32b_0/src/params/ddr3_sdram_mem_params.v
source/ip/ddr3_32b_0/ddr_p_eval/ddr3_32b_0/src/rtl/
source/ip/ddr3_32b_0/ddr_p_eval/ddr3_32b_0/src/rtl/top/
source/ip/ddr3_32b_0/ddr_p_eval/ddr3_32b_0/src/rtl/top/ecp3/
source/ip/ddr3_32b_0/ddr_p_eval/ddr3_32b_0/src/rtl/top/ecp3/ddr3_sdram_mem_top_wrapper.v
source/ip/ddr3_32b_0/ddr_p_eval/eval_sim_readme.txt
source/ip/ddr3_32b_0/ddr_p_eval/models/
source/ip/ddr3_32b_0/ddr_p_eval/models/ecp3/
source/ip/ddr3_32b_0/ddr_p_eval/models/ecp3/clk_phase.v
source/ip/ddr3_32b_0/ddr_p_eval/models/ecp3/clk_stop.v
source/ip/ddr3_32b_0/ddr_p_eval/models/ecp3/ddr3_clks.v
source/ip/ddr3_32b_0/ddr_p_eval/models/ecp3/ddr3_pll.v
source/ip/ddr3_32b_0/ddr_p_eval/models/ecp3/jitter_filter.v
source/ip/ddr3_32b_0/ddr_p_eval/models/ecp3/pll_control.v
source/ip/ddr3_32b_0/ddr_p_eval/models/ecp3/pmi_def.v
source/ip/ddr3_32b_0/ddr_p_eval/models/ecp3/pmi_distributed_dpram.v
source/ip/ddr3_32b_0/ddr_p_eval/models/mem/
source/ip/ddr3_32b_0/ddr_p_eval/models/mem/ddr3.v
source/ip/ddr3_32b_0/ddr_p_eval/models/mem/ddr3_dimm_32.v
source/ip/ddr3_32b_0/ddr_p_eval/models/mem/ddr3_parameters.vh
source/ip/ddr3_32b_0/ddr_p_eval/Readme.htm
source/ip/ddr3_32b_0/ddr_p_eval/testbench/
source/ip/ddr3_32b_0/ddr_p_eval/testbench/tests/
source/i

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