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文件名称:AWGN_VerilogDesign-master

  • 所属分类：
    VHDL-FPGA-Verilog
  • 标签属性：
    [VHDL] [源码]
  • 上传时间：
    2016-12-06
  • 文件大小：
    866kb
  • 已下载：
    3次
  • 提 供 者：
    冰城杨****
  • 相关连接：
    无
  • 下载说明：
    别用迅雷下载，失败请重下，重下不扣分！
修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

加性高斯白噪声生成的VERILOG实现，包含所有的testbench文件。可直接使用-Additive white gaussian noise generated VERILOG realized, including all testbench files. Can be used directly
(系统自动生成,下载前可以参看下载内容)

下载文件列表

AWGN_VerilogDesign-master/
AWGN_VerilogDesign-master/AWGN.v
AWGN_VerilogDesign-master/AWGN_tb.v
AWGN_VerilogDesign-master/Ce.dat
AWGN_VerilogDesign-master/Cf.dat
AWGN_VerilogDesign-master/Cg.dat
AWGN_VerilogDesign-master/Concat.v
AWGN_VerilogDesign-master/Log.v
AWGN_VerilogDesign-master/Log_tb.v
AWGN_VerilogDesign-master/Log_test_in.dat
AWGN_VerilogDesign-master/Log_test_out.dat
AWGN_VerilogDesign-master/Mult.v
AWGN_VerilogDesign-master/Mult_tb.v
AWGN_VerilogDesign-master/Sincos.v
AWGN_VerilogDesign-master/Sincos_tb.v
AWGN_VerilogDesign-master/Sincos_test_in.dat
AWGN_VerilogDesign-master/Sincos_test_out1.dat
AWGN_VerilogDesign-master/Sincos_test_out2.dat
AWGN_VerilogDesign-master/Split.v
AWGN_VerilogDesign-master/Sqrt.v
AWGN_VerilogDesign-master/Sqrt_tb.v
AWGN_VerilogDesign-master/Sqrt_test_in.dat
AWGN_VerilogDesign-master/Sqrt_test_out.dat
AWGN_VerilogDesign-master/TWs_test_in.dat
AWGN_VerilogDesign-master/TWs_test_out.dat
AWGN_VerilogDesign-master/Tausworthe.v
AWGN_VerilogDesign-master/Tausworthe_tb.v
AWGN_VerilogDesign-master/mat_data_in1.dat
AWGN_VerilogDesign-master/mat_data_in2.dat
AWGN_VerilogDesign-master/mat_data_in3.dat
AWGN_VerilogDesign-master/mat_data_in4.dat
AWGN_VerilogDesign-master/mat_data_in5.dat
AWGN_VerilogDesign-master/mat_data_in6.dat
AWGN_VerilogDesign-master/mat_data_out1.dat
AWGN_VerilogDesign-master/mat_data_out2.dat
AWGN_VerilogDesign-master/mat_test_out.dat
AWGN_VerilogDesign-master/mult_test_in1.dat
AWGN_VerilogDesign-master/mult_test_in2.dat
AWGN_VerilogDesign-master/mult_test_out.dat
AWGN_VerilogDesign-master/new_urng.mat
AWGN_VerilogDesign-master/verilog_data_out.dat
AWGN_VerilogDesign-master/work/
AWGN_VerilogDesign-master/work/@a@w@g@n/
AWGN_VerilogDesign-master/work/@a@w@g@n/_primary.dat
AWGN_VerilogDesign-master/work/@a@w@g@n/_primary.dbs
AWGN_VerilogDesign-master/work/@a@w@g@n/_primary.vhd
AWGN_VerilogDesign-master/work/@a@w@g@n_tb/
AWGN_VerilogDesign-master/work/@a@w@g@n_tb/_primary.dat
AWGN_VerilogDesign-master/work/@a@w@g@n_tb/_primary.dbs
AWGN_VerilogDesign-master/work/@a@w@g@n_tb/_primary.vhd
AWGN_VerilogDesign-master/work/@concat/
AWGN_VerilogDesign-master/work/@concat/_primary.dat
AWGN_VerilogDesign-master/work/@concat/_primary.dbs
AWGN_VerilogDesign-master/work/@concat/_primary.vhd
AWGN_VerilogDesign-master/work/@log/
AWGN_VerilogDesign-master/work/@log/_primary.dat
AWGN_VerilogDesign-master/work/@log/_primary.dbs
AWGN_VerilogDesign-master/work/@log/_primary.vhd
AWGN_VerilogDesign-master/work/@log_tb/
AWGN_VerilogDesign-master/work/@log_tb/_primary.dat
AWGN_VerilogDesign-master/work/@log_tb/_primary.dbs
AWGN_VerilogDesign-master/work/@log_tb/_primary.vhd
AWGN_VerilogDesign-master/work/@mult/
AWGN_VerilogDesign-master/work/@mult/_primary.dat
AWGN_VerilogDesign-master/work/@mult/_primary.dbs
AWGN_VerilogDesign-master/work/@mult/_primary.vhd
AWGN_VerilogDesign-master/work/@mult_tb/
AWGN_VerilogDesign-master/work/@mult_tb/_primary.dat
AWGN_VerilogDesign-master/work/@mult_tb/_primary.dbs
AWGN_VerilogDesign-master/work/@mult_tb/_primary.vhd
AWGN_VerilogDesign-master/work/@sincos/
AWGN_VerilogDesign-master/work/@sincos/_primary.dat
AWGN_VerilogDesign-master/work/@sincos/_primary.dbs
AWGN_VerilogDesign-master/work/@sincos/_primary.vhd
AWGN_VerilogDesign-master/work/@sincos_tb/
AWGN_VerilogDesign-master/work/@sincos_tb/_primary.dat
AWGN_VerilogDesign-master/work/@sincos_tb/_primary.dbs
AWGN_VerilogDesign-master/work/@sincos_tb/_primary.vhd
AWGN_VerilogDesign-master/work/@split/
AWGN_VerilogDesign-master/work/@split/_primary.dat
AWGN_VerilogDesign-master/work/@split/_primary.dbs
AWGN_VerilogDesign-master/work/@split/_primary.vhd
AWGN_VerilogDesign-master/work/@sqrt/
AWGN_VerilogDesign-master/work/@sqrt/_primary.dat
AWGN_VerilogDesign-master/work/@sqrt/_primary.dbs
AWGN_VerilogDesign-master/work/@sqrt/_primary.vhd
AWGN_VerilogDesign-master/work/@sqrt_tb/
AWGN_VerilogDesign-master/work/@sqrt_tb/_primary.dat
AWGN_VerilogDesign-master/work/@sqrt_tb/_primary.dbs
AWGN_VerilogDesign-master/work/@sqrt_tb/_primary.vhd
AWGN_VerilogDesign-master/work/@tausworthe/
AWGN_VerilogDesign-master/work/@tausworthe/_primary.dat
AWGN_VerilogDesign-master/work/@tausworthe/_primary.dbs
AWGN_VerilogDesign-master/work/@tausworthe/_primary.vhd
AWGN_VerilogDesign-master/work/@tausworthe_tb/
AWGN_VerilogDesign-master/work/@tausworthe_tb/_primary.dat
AWGN_VerilogDesign-master/work/@tausworthe_tb/_primary.dbs
AWGN_VerilogDesign-master/work/@tausworthe_tb/_primary.vhd
AWGN_VerilogDesign-master/work/_info
AWGN_VerilogDesign-master/work/_vmake

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