文件名称:cic_design
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采用CIC(级联积分梳状)滤波器实现降采样的功能,并分析了级联级数、差分延时数对CIC滤波器幅频响应的影响;采用Verilog语言实现了CIC滤波及降采样的功能;-Using CIC (Cascaded Integrator Comb) filter down-sampling function, and analyzes cascaded stages, affecting the number of differential delay CIC filter amplitude-frequency response using Verilog language of the CIC filter and down sampling Features
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下载文件列表
cic_design.v
tbw_cic3.v
CIC_foundation.m
CIC_Multirate.m
tbw_cic3.v
CIC_foundation.m
CIC_Multirate.m
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