文件名称:led
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- 上传时间:2016-12-11
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文件大小:310.35kb
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简单程序,led流水灯设计,基于移位操作-Simple procedures, led water lamp design, based on the shift operation
(系统自动生成,下载前可以参看下载内容)
下载文件列表
led/
led/db/
led/db/led.(0).cnf.cdb
led/db/led.(0).cnf.hdb
led/db/led.asm.qmsg
led/db/led.asm.rdb
led/db/led.cbx.xml
led/db/led.cmp.bpm
led/db/led.cmp.cdb
led/db/led.cmp.hdb
led/db/led.cmp.idb
led/db/led.cmp.kpt
led/db/led.cmp.logdb
led/db/led.cmp.rdb
led/db/led.cmp0.ddb
led/db/led.cmp1.ddb
led/db/led.cmp_merge.kpt
led/db/led.db_info
led/db/led.eda.qmsg
led/db/led.fit.qmsg
led/db/led.hier_info
led/db/led.hif
led/db/led.ipinfo
led/db/led.lpc.html
led/db/led.lpc.rdb
led/db/led.lpc.txt
led/db/led.map.ammdb
led/db/led.map.bpm
led/db/led.map.cdb
led/db/led.map.hdb
led/db/led.map.kpt
led/db/led.map.logdb
led/db/led.map.qmsg
led/db/led.map.rdb
led/db/led.map_bb.cdb
led/db/led.map_bb.hdb
led/db/led.map_bb.logdb
led/db/led.pplq.rdb
led/db/led.pre_map.hdb
led/db/led.pti_db_list.ddb
led/db/led.root_partition.map.reg_db.cdb
led/db/led.routing.rdb
led/db/led.rpp.qmsg
led/db/led.rtlv.hdb
led/db/led.rtlv_sg.cdb
led/db/led.rtlv_sg_swap.cdb
led/db/led.sgate.rvd
led/db/led.sgate_sm.rvd
led/db/led.sgdiff.cdb
led/db/led.sgdiff.hdb
led/db/led.sld_design_entry.sci
led/db/led.sld_design_entry_dsc.sci
led/db/led.smart_action.txt
led/db/led.sta.qmsg
led/db/led.sta.rdb
led/db/led.sta_cmp.6_slow.tdb
led/db/led.syn_hier_info
led/db/led.tis_db_list.ddb
led/db/led.tmw_info
led/db/led.vpr.ammdb
led/db/logic_util_heursitic.dat
led/db/prev_cmp_led.qmsg
led/incremental_db/
led/incremental_db/README
led/incremental_db/compiled_partitions/
led/incremental_db/compiled_partitions/led.db_info
led/incremental_db/compiled_partitions/led.root_partition.cmp.ammdb
led/incremental_db/compiled_partitions/led.root_partition.cmp.cdb
led/incremental_db/compiled_partitions/led.root_partition.cmp.dfp
led/incremental_db/compiled_partitions/led.root_partition.cmp.hdb
led/incremental_db/compiled_partitions/led.root_partition.cmp.kpt
led/incremental_db/compiled_partitions/led.root_partition.cmp.logdb
led/incremental_db/compiled_partitions/led.root_partition.cmp.rcfdb
led/incremental_db/compiled_partitions/led.root_partition.map.cdb
led/incremental_db/compiled_partitions/led.root_partition.map.dpi
led/incremental_db/compiled_partitions/led.root_partition.map.hbdb.cdb
led/incremental_db/compiled_partitions/led.root_partition.map.hbdb.hb_info
led/incremental_db/compiled_partitions/led.root_partition.map.hbdb.hdb
led/incremental_db/compiled_partitions/led.root_partition.map.hbdb.sig
led/incremental_db/compiled_partitions/led.root_partition.map.hdb
led/incremental_db/compiled_partitions/led.root_partition.map.kpt
led/led.qpf
led/led.qsf
led/led.qws
led/led.v
led/led_nativelink_simulation.rpt
led/led_tb.v
led/output_files/
led/output_files/led.asm.rpt
led/output_files/led.done
led/output_files/led.eda.rpt
led/output_files/led.fit.rpt
led/output_files/led.fit.smsg
led/output_files/led.fit.summary
led/output_files/led.flow.rpt
led/output_files/led.map.rpt
led/output_files/led.map.summary
led/output_files/led.pin
led/output_files/led.sta.rpt
led/output_files/led.sta.summary
led/simulation/
led/simulation/modelsim/
led/simulation/modelsim/led.sft
led/simulation/modelsim/led.vo
led/simulation/modelsim/led_fast.vo
led/simulation/modelsim/led_modelsim.xrf
led/simulation/modelsim/led_run_msim_rtl_verilog.do
led/simulation/modelsim/led_v.sdo
led/simulation/modelsim/led_v_fast.sdo
led/simulation/modelsim/modelsim.ini
led/simulation/modelsim/msim_transcript
led/simulation/modelsim/rtl_work/
led/simulation/modelsim/rtl_work/_info
led/simulation/modelsim/rtl_work/_temp/
led/simulation/modelsim/rtl_work/_vmake
led/simulation/modelsim/rtl_work/led/
led/simulation/modelsim/rtl_work/led/_primary.dat
led/simulation/modelsim/rtl_work/led/_primary.dbs
led/simulation/modelsim/rtl_work/led/_primary.vhd
led/simulation/modelsim/rtl_work/led/verilog.prw
led/simulation/modelsim/rtl_work/led/verilog.psm
led/simulation/modelsim/rtl_work/led_tb/
led/simulation/modelsim/rtl_work/led_tb/_primary.dat
led/simulation/modelsim/rtl_work/led_tb/_primary.dbs
led/simulation/modelsim/rtl_work/led_tb/_primary.vhd
led/simulation/modelsim/rtl_work/led_tb/verilog.prw
led/simulation/modelsim/rtl_work/led_tb/verilog.psm
led/simulation/modelsim/vsim.wlf
led/db/
led/db/led.(0).cnf.cdb
led/db/led.(0).cnf.hdb
led/db/led.asm.qmsg
led/db/led.asm.rdb
led/db/led.cbx.xml
led/db/led.cmp.bpm
led/db/led.cmp.cdb
led/db/led.cmp.hdb
led/db/led.cmp.idb
led/db/led.cmp.kpt
led/db/led.cmp.logdb
led/db/led.cmp.rdb
led/db/led.cmp0.ddb
led/db/led.cmp1.ddb
led/db/led.cmp_merge.kpt
led/db/led.db_info
led/db/led.eda.qmsg
led/db/led.fit.qmsg
led/db/led.hier_info
led/db/led.hif
led/db/led.ipinfo
led/db/led.lpc.html
led/db/led.lpc.rdb
led/db/led.lpc.txt
led/db/led.map.ammdb
led/db/led.map.bpm
led/db/led.map.cdb
led/db/led.map.hdb
led/db/led.map.kpt
led/db/led.map.logdb
led/db/led.map.qmsg
led/db/led.map.rdb
led/db/led.map_bb.cdb
led/db/led.map_bb.hdb
led/db/led.map_bb.logdb
led/db/led.pplq.rdb
led/db/led.pre_map.hdb
led/db/led.pti_db_list.ddb
led/db/led.root_partition.map.reg_db.cdb
led/db/led.routing.rdb
led/db/led.rpp.qmsg
led/db/led.rtlv.hdb
led/db/led.rtlv_sg.cdb
led/db/led.rtlv_sg_swap.cdb
led/db/led.sgate.rvd
led/db/led.sgate_sm.rvd
led/db/led.sgdiff.cdb
led/db/led.sgdiff.hdb
led/db/led.sld_design_entry.sci
led/db/led.sld_design_entry_dsc.sci
led/db/led.smart_action.txt
led/db/led.sta.qmsg
led/db/led.sta.rdb
led/db/led.sta_cmp.6_slow.tdb
led/db/led.syn_hier_info
led/db/led.tis_db_list.ddb
led/db/led.tmw_info
led/db/led.vpr.ammdb
led/db/logic_util_heursitic.dat
led/db/prev_cmp_led.qmsg
led/incremental_db/
led/incremental_db/README
led/incremental_db/compiled_partitions/
led/incremental_db/compiled_partitions/led.db_info
led/incremental_db/compiled_partitions/led.root_partition.cmp.ammdb
led/incremental_db/compiled_partitions/led.root_partition.cmp.cdb
led/incremental_db/compiled_partitions/led.root_partition.cmp.dfp
led/incremental_db/compiled_partitions/led.root_partition.cmp.hdb
led/incremental_db/compiled_partitions/led.root_partition.cmp.kpt
led/incremental_db/compiled_partitions/led.root_partition.cmp.logdb
led/incremental_db/compiled_partitions/led.root_partition.cmp.rcfdb
led/incremental_db/compiled_partitions/led.root_partition.map.cdb
led/incremental_db/compiled_partitions/led.root_partition.map.dpi
led/incremental_db/compiled_partitions/led.root_partition.map.hbdb.cdb
led/incremental_db/compiled_partitions/led.root_partition.map.hbdb.hb_info
led/incremental_db/compiled_partitions/led.root_partition.map.hbdb.hdb
led/incremental_db/compiled_partitions/led.root_partition.map.hbdb.sig
led/incremental_db/compiled_partitions/led.root_partition.map.hdb
led/incremental_db/compiled_partitions/led.root_partition.map.kpt
led/led.qpf
led/led.qsf
led/led.qws
led/led.v
led/led_nativelink_simulation.rpt
led/led_tb.v
led/output_files/
led/output_files/led.asm.rpt
led/output_files/led.done
led/output_files/led.eda.rpt
led/output_files/led.fit.rpt
led/output_files/led.fit.smsg
led/output_files/led.fit.summary
led/output_files/led.flow.rpt
led/output_files/led.map.rpt
led/output_files/led.map.summary
led/output_files/led.pin
led/output_files/led.sta.rpt
led/output_files/led.sta.summary
led/simulation/
led/simulation/modelsim/
led/simulation/modelsim/led.sft
led/simulation/modelsim/led.vo
led/simulation/modelsim/led_fast.vo
led/simulation/modelsim/led_modelsim.xrf
led/simulation/modelsim/led_run_msim_rtl_verilog.do
led/simulation/modelsim/led_v.sdo
led/simulation/modelsim/led_v_fast.sdo
led/simulation/modelsim/modelsim.ini
led/simulation/modelsim/msim_transcript
led/simulation/modelsim/rtl_work/
led/simulation/modelsim/rtl_work/_info
led/simulation/modelsim/rtl_work/_temp/
led/simulation/modelsim/rtl_work/_vmake
led/simulation/modelsim/rtl_work/led/
led/simulation/modelsim/rtl_work/led/_primary.dat
led/simulation/modelsim/rtl_work/led/_primary.dbs
led/simulation/modelsim/rtl_work/led/_primary.vhd
led/simulation/modelsim/rtl_work/led/verilog.prw
led/simulation/modelsim/rtl_work/led/verilog.psm
led/simulation/modelsim/rtl_work/led_tb/
led/simulation/modelsim/rtl_work/led_tb/_primary.dat
led/simulation/modelsim/rtl_work/led_tb/_primary.dbs
led/simulation/modelsim/rtl_work/led_tb/_primary.vhd
led/simulation/modelsim/rtl_work/led_tb/verilog.prw
led/simulation/modelsim/rtl_work/led_tb/verilog.psm
led/simulation/modelsim/vsim.wlf
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