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文件名称:seg

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    2016-12-11
  • 文件大小:
    333.13kb
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介绍说明--下载内容来自于网络,使用问题请自行百度

FPGA简单程序,可实现一位数码管显示,从0到9 的循环显示-FPGA simple program, enabling a digital display, the display cycles 0-9
(系统自动生成,下载前可以参看下载内容)

下载文件列表

seg/
seg/db/
seg/db/logic_util_heursitic.dat
seg/db/prev_cmp_seg.qmsg
seg/db/seg.(0).cnf.cdb
seg/db/seg.(0).cnf.hdb
seg/db/seg.asm.qmsg
seg/db/seg.asm.rdb
seg/db/seg.cbx.xml
seg/db/seg.cmp.idb
seg/db/seg.cmp.kpt
seg/db/seg.cmp.rdb
seg/db/seg.cmp0.ddb
seg/db/seg.cmp1.ddb
seg/db/seg.cmp_merge.kpt
seg/db/seg.db_info
seg/db/seg.eda.qmsg
seg/db/seg.fit.qmsg
seg/db/seg.hier_info
seg/db/seg.hif
seg/db/seg.ipinfo
seg/db/seg.lpc.html
seg/db/seg.lpc.rdb
seg/db/seg.lpc.txt
seg/db/seg.map.ammdb
seg/db/seg.map.bpm
seg/db/seg.map.cdb
seg/db/seg.map.hdb
seg/db/seg.map.kpt
seg/db/seg.map.logdb
seg/db/seg.map.qmsg
seg/db/seg.map.rdb
seg/db/seg.map_bb.cdb
seg/db/seg.map_bb.hdb
seg/db/seg.map_bb.logdb
seg/db/seg.pplq.rdb
seg/db/seg.pre_map.hdb
seg/db/seg.pti_db_list.ddb
seg/db/seg.root_partition.map.reg_db.cdb
seg/db/seg.routing.rdb
seg/db/seg.rtlv.hdb
seg/db/seg.rtlv_sg.cdb
seg/db/seg.rtlv_sg_swap.cdb
seg/db/seg.sgdiff.cdb
seg/db/seg.sgdiff.hdb
seg/db/seg.sld_design_entry.sci
seg/db/seg.sld_design_entry_dsc.sci
seg/db/seg.smart_action.txt
seg/db/seg.sta.qmsg
seg/db/seg.sta.rdb
seg/db/seg.syn_hier_info
seg/db/seg.tis_db_list.ddb
seg/db/seg.tmw_info
seg/db/seg.vpr.ammdb
seg/incremental_db/
seg/incremental_db/README
seg/incremental_db/compiled_partitions/
seg/incremental_db/compiled_partitions/seg.db_info
seg/incremental_db/compiled_partitions/seg.root_partition.cmp.ammdb
seg/incremental_db/compiled_partitions/seg.root_partition.cmp.cdb
seg/incremental_db/compiled_partitions/seg.root_partition.cmp.dfp
seg/incremental_db/compiled_partitions/seg.root_partition.cmp.hdb
seg/incremental_db/compiled_partitions/seg.root_partition.cmp.kpt
seg/incremental_db/compiled_partitions/seg.root_partition.cmp.logdb
seg/incremental_db/compiled_partitions/seg.root_partition.cmp.rcfdb
seg/incremental_db/compiled_partitions/seg.root_partition.map.cdb
seg/incremental_db/compiled_partitions/seg.root_partition.map.dpi
seg/incremental_db/compiled_partitions/seg.root_partition.map.hbdb.cdb
seg/incremental_db/compiled_partitions/seg.root_partition.map.hbdb.hb_info
seg/incremental_db/compiled_partitions/seg.root_partition.map.hbdb.hdb
seg/incremental_db/compiled_partitions/seg.root_partition.map.hbdb.sig
seg/incremental_db/compiled_partitions/seg.root_partition.map.hdb
seg/incremental_db/compiled_partitions/seg.root_partition.map.kpt
seg/output_files/
seg/output_files/Chain3.cdf
seg/output_files/output_files/
seg/output_files/seg.asm.rpt
seg/output_files/seg.done
seg/output_files/seg.eda.rpt
seg/output_files/seg.fit.rpt
seg/output_files/seg.fit.smsg
seg/output_files/seg.fit.summary
seg/output_files/seg.flow.rpt
seg/output_files/seg.jdi
seg/output_files/seg.map.rpt
seg/output_files/seg.map.smsg
seg/output_files/seg.map.summary
seg/output_files/seg.pin
seg/output_files/seg.pof
seg/output_files/seg.sof
seg/output_files/seg.sta.rpt
seg/output_files/seg.sta.summary
seg/seg.qpf
seg/seg.qsf
seg/seg.qws
seg/seg.v
seg/seg.v.bak
seg/seg_nativelink_simulation.rpt
seg/segtestbench.v
seg/segtestbench.v.bak
seg/simulation/
seg/simulation/modelsim/
seg/simulation/modelsim/modelsim.ini
seg/simulation/modelsim/msim_transcript
seg/simulation/modelsim/rtl_work/
seg/simulation/modelsim/rtl_work/_info
seg/simulation/modelsim/rtl_work/_temp/
seg/simulation/modelsim/rtl_work/_vmake
seg/simulation/modelsim/rtl_work/seg/
seg/simulation/modelsim/rtl_work/seg/_primary.dat
seg/simulation/modelsim/rtl_work/seg/_primary.dbs
seg/simulation/modelsim/rtl_work/seg/_primary.vhd
seg/simulation/modelsim/rtl_work/seg/verilog.prw
seg/simulation/modelsim/rtl_work/seg/verilog.psm
seg/simulation/modelsim/rtl_work/segtestbench/
seg/simulation/modelsim/rtl_work/segtestbench/_primary.dat
seg/simulation/modelsim/rtl_work/segtestbench/_primary.dbs
seg/simulation/modelsim/rtl_work/segtestbench/_primary.vhd
seg/simulation/modelsim/rtl_work/segtestbench/verilog.prw
seg/simulation/modelsim/rtl_work/segtestbench/verilog.psm
seg/simulation/modelsim/seg.sft
seg/simulation/modelsim/seg.vo
seg/simulation/modelsim/seg_fast.vo
seg/simulation/modelsim/seg_modelsim.xrf
seg/simulation/modelsim/seg_run_msim_rtl_verilog.do
seg/simulation/modelsim/seg_run_msim_rtl_verilog.do.bak
seg/simulation/modelsim/seg_run_msim_rtl_verilog.do.bak1
seg/simulation/modelsim/seg_run_msim_rtl_verilog.do.bak2
seg/simulation/modelsim/seg_run_msim_rtl_verilog.do.bak3
seg/simulation/modelsim/seg_run_msim_rtl_verilog.do.bak4
seg/simulation/modelsim/seg_run_msim_rtl_verilog.do.bak5
seg/simulation/modelsim/seg_run_msim_rtl_verilog.do.bak6
seg/simulation/modelsim/seg_run_msim_rtl_verilog.do.bak7
seg/simulation/modelsim/seg_v.sdo
seg/simulation/modelsim/seg_v_fast.sdo
seg/simulation/modelsim/vsim.wlf

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