文件名称:VDMA
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- 上传时间：2016-12-24
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文件大小：296.6kb
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zynq7000平台上的vdma应用实例，适用于PL部分到 PS部分的高速图像传输。-vdma example on zynq7000， which is very useful to image communications between PL and PS
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下载文件列表
VDMA/VDMA.cache/wt/java_command_handlers.wdf
VDMA/VDMA.cache/wt/project.wpc
VDMA/VDMA.cache/wt/webtalk_pa.xml
VDMA/VDMA.hw/VDMA.lpr
VDMA/VDMA.hw/webtalk/.xsim_webtallk.info
VDMA/VDMA.hw/webtalk/labtool_webtalk.log
VDMA/VDMA.hw/webtalk/usage_statistics_ext_labtool.html
VDMA/VDMA.hw/webtalk/usage_statistics_ext_labtool.xml
VDMA/VDMA.srcs/sources_1/bd/design_1/design_1.bd
VDMA/VDMA.srcs/sources_1/bd/design_1/design_1.bxml
VDMA/VDMA.srcs/sources_1/bd/design_1/ip/design_1_axi_mem_intercon_0/design_1_axi_mem_intercon_0.xci
VDMA/VDMA.srcs/sources_1/bd/design_1/ip/design_1_axi_mem_intercon_0/design_1_axi_mem_intercon_0.xml
VDMA/VDMA.srcs/sources_1/bd/design_1/ip/design_1_axi_vdma_0_0/design_1_axi_vdma_0_0.xci
VDMA/VDMA.srcs/sources_1/bd/design_1/ip/design_1_axi_vdma_0_0/design_1_axi_vdma_0_0.xml
VDMA/VDMA.srcs/sources_1/bd/design_1/ip/design_1_ila_0_0/design_1_ila_0_0.xci
VDMA/VDMA.srcs/sources_1/bd/design_1/ip/design_1_ila_0_0/design_1_ila_0_0.xml
VDMA/VDMA.srcs/sources_1/bd/design_1/ip/design_1_ila_1_0/design_1_ila_1_0.xci
VDMA/VDMA.srcs/sources_1/bd/design_1/ip/design_1_ila_1_0/design_1_ila_1_0.xml
VDMA/VDMA.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0.xci
VDMA/VDMA.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0.xml
VDMA/VDMA.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_axi_periph_0/design_1_processing_system7_0_axi_periph_0.xci
VDMA/VDMA.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_axi_periph_0/design_1_processing_system7_0_axi_periph_0.xml
VDMA/VDMA.srcs/sources_1/bd/design_1/ip/design_1_rst_processing_system7_0_50M_0/design_1_rst_processing_system7_0_50M_0.xci
VDMA/VDMA.srcs/sources_1/bd/design_1/ip/design_1_rst_processing_system7_0_50M_0/design_1_rst_processing_system7_0_50M_0.xml
VDMA/VDMA.srcs/sources_1/bd/design_1/ip/design_1_v_tpg_0_0/design_1_v_tpg_0_0.xci
VDMA/VDMA.srcs/sources_1/bd/design_1/ip/design_1_v_tpg_0_0/design_1_v_tpg_0_0.xml
VDMA/VDMA.srcs/sources_1/bd/design_1/ip/design_1_xbar_0/design_1_xbar_0.xci
VDMA/VDMA.srcs/sources_1/bd/design_1/ip/design_1_xbar_0/design_1_xbar_0.xml
VDMA/VDMA.srcs/sources_1/bd/design_1/ip/design_1_xbar_1/design_1_xbar_1.xci
VDMA/VDMA.srcs/sources_1/bd/design_1/ip/design_1_xbar_1/design_1_xbar_1.xml
VDMA/VDMA.srcs/sources_1/bd/design_1/ui/bd_1f5defd0.ui
VDMA/VDMA.xpr
VDMA/VDMA.srcs/sources_1/bd/design_1/ip/design_1_axi_mem_intercon_0
VDMA/VDMA.srcs/sources_1/bd/design_1/ip/design_1_axi_vdma_0_0
VDMA/VDMA.srcs/sources_1/bd/design_1/ip/design_1_ila_0_0
VDMA/VDMA.srcs/sources_1/bd/design_1/ip/design_1_ila_1_0
VDMA/VDMA.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0
VDMA/VDMA.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_axi_periph_0
VDMA/VDMA.srcs/sources_1/bd/design_1/ip/design_1_rst_processing_system7_0_50M_0
VDMA/VDMA.srcs/sources_1/bd/design_1/ip/design_1_v_tpg_0_0
VDMA/VDMA.srcs/sources_1/bd/design_1/ip/design_1_xbar_0
VDMA/VDMA.srcs/sources_1/bd/design_1/ip/design_1_xbar_1
VDMA/VDMA.srcs/sources_1/bd/design_1/ip
VDMA/VDMA.srcs/sources_1/bd/design_1/ui
VDMA/VDMA.srcs/sources_1/bd/design_1
VDMA/VDMA.cache/compile_simlib/activehdl
VDMA/VDMA.cache/compile_simlib/ies
VDMA/VDMA.cache/compile_simlib/modelsim
VDMA/VDMA.cache/compile_simlib/questa
VDMA/VDMA.cache/compile_simlib/riviera
VDMA/VDMA.cache/compile_simlib/vcs
VDMA/VDMA.srcs/sources_1/bd
VDMA/VDMA.cache/compile_simlib
VDMA/VDMA.cache/wt
VDMA/VDMA.hw/webtalk
VDMA/VDMA.ip_user_files/ipstatic
VDMA/VDMA.srcs/sources_1
VDMA/VDMA.cache
VDMA/VDMA.hw
VDMA/VDMA.ip_user_files
VDMA/VDMA.sim
VDMA/VDMA.srcs
VDMA
VDMA/VDMA.cache/wt/project.wpc
VDMA/VDMA.cache/wt/webtalk_pa.xml
VDMA/VDMA.hw/VDMA.lpr
VDMA/VDMA.hw/webtalk/.xsim_webtallk.info
VDMA/VDMA.hw/webtalk/labtool_webtalk.log
VDMA/VDMA.hw/webtalk/usage_statistics_ext_labtool.html
VDMA/VDMA.hw/webtalk/usage_statistics_ext_labtool.xml
VDMA/VDMA.srcs/sources_1/bd/design_1/design_1.bd
VDMA/VDMA.srcs/sources_1/bd/design_1/design_1.bxml
VDMA/VDMA.srcs/sources_1/bd/design_1/ip/design_1_axi_mem_intercon_0/design_1_axi_mem_intercon_0.xci
VDMA/VDMA.srcs/sources_1/bd/design_1/ip/design_1_axi_mem_intercon_0/design_1_axi_mem_intercon_0.xml
VDMA/VDMA.srcs/sources_1/bd/design_1/ip/design_1_axi_vdma_0_0/design_1_axi_vdma_0_0.xci
VDMA/VDMA.srcs/sources_1/bd/design_1/ip/design_1_axi_vdma_0_0/design_1_axi_vdma_0_0.xml
VDMA/VDMA.srcs/sources_1/bd/design_1/ip/design_1_ila_0_0/design_1_ila_0_0.xci
VDMA/VDMA.srcs/sources_1/bd/design_1/ip/design_1_ila_0_0/design_1_ila_0_0.xml
VDMA/VDMA.srcs/sources_1/bd/design_1/ip/design_1_ila_1_0/design_1_ila_1_0.xci
VDMA/VDMA.srcs/sources_1/bd/design_1/ip/design_1_ila_1_0/design_1_ila_1_0.xml
VDMA/VDMA.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0.xci
VDMA/VDMA.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0.xml
VDMA/VDMA.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_axi_periph_0/design_1_processing_system7_0_axi_periph_0.xci
VDMA/VDMA.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_axi_periph_0/design_1_processing_system7_0_axi_periph_0.xml
VDMA/VDMA.srcs/sources_1/bd/design_1/ip/design_1_rst_processing_system7_0_50M_0/design_1_rst_processing_system7_0_50M_0.xci
VDMA/VDMA.srcs/sources_1/bd/design_1/ip/design_1_rst_processing_system7_0_50M_0/design_1_rst_processing_system7_0_50M_0.xml
VDMA/VDMA.srcs/sources_1/bd/design_1/ip/design_1_v_tpg_0_0/design_1_v_tpg_0_0.xci
VDMA/VDMA.srcs/sources_1/bd/design_1/ip/design_1_v_tpg_0_0/design_1_v_tpg_0_0.xml
VDMA/VDMA.srcs/sources_1/bd/design_1/ip/design_1_xbar_0/design_1_xbar_0.xci
VDMA/VDMA.srcs/sources_1/bd/design_1/ip/design_1_xbar_0/design_1_xbar_0.xml
VDMA/VDMA.srcs/sources_1/bd/design_1/ip/design_1_xbar_1/design_1_xbar_1.xci
VDMA/VDMA.srcs/sources_1/bd/design_1/ip/design_1_xbar_1/design_1_xbar_1.xml
VDMA/VDMA.srcs/sources_1/bd/design_1/ui/bd_1f5defd0.ui
VDMA/VDMA.xpr
VDMA/VDMA.srcs/sources_1/bd/design_1/ip/design_1_axi_mem_intercon_0
VDMA/VDMA.srcs/sources_1/bd/design_1/ip/design_1_axi_vdma_0_0
VDMA/VDMA.srcs/sources_1/bd/design_1/ip/design_1_ila_0_0
VDMA/VDMA.srcs/sources_1/bd/design_1/ip/design_1_ila_1_0
VDMA/VDMA.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0
VDMA/VDMA.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_axi_periph_0
VDMA/VDMA.srcs/sources_1/bd/design_1/ip/design_1_rst_processing_system7_0_50M_0
VDMA/VDMA.srcs/sources_1/bd/design_1/ip/design_1_v_tpg_0_0
VDMA/VDMA.srcs/sources_1/bd/design_1/ip/design_1_xbar_0
VDMA/VDMA.srcs/sources_1/bd/design_1/ip/design_1_xbar_1
VDMA/VDMA.srcs/sources_1/bd/design_1/ip
VDMA/VDMA.srcs/sources_1/bd/design_1/ui
VDMA/VDMA.srcs/sources_1/bd/design_1
VDMA/VDMA.cache/compile_simlib/activehdl
VDMA/VDMA.cache/compile_simlib/ies
VDMA/VDMA.cache/compile_simlib/modelsim
VDMA/VDMA.cache/compile_simlib/questa
VDMA/VDMA.cache/compile_simlib/riviera
VDMA/VDMA.cache/compile_simlib/vcs
VDMA/VDMA.srcs/sources_1/bd
VDMA/VDMA.cache/compile_simlib
VDMA/VDMA.cache/wt
VDMA/VDMA.hw/webtalk
VDMA/VDMA.ip_user_files/ipstatic
VDMA/VDMA.srcs/sources_1
VDMA/VDMA.cache
VDMA/VDMA.hw
VDMA/VDMA.ip_user_files
VDMA/VDMA.sim
VDMA/VDMA.srcs
VDMA
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