文件名称:ad9226_verilog
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- 上传时间:2017-02-06
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文件大小:2.62mb
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AD9226在Sparten6上的FPGA代码实现,测试通过。-AD9226 Sparten6 FPGA code on the test, the adoption.
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下载文件列表
ad9226_verilog/
ad9226_verilog/.Xil/
ad9226_verilog/AD_summary.html
ad9226_verilog/_ngo/
ad9226_verilog/_ngo/netlist.lst
ad9226_verilog/_xmsgs/
ad9226_verilog/_xmsgs/bitgen.xmsgs
ad9226_verilog/_xmsgs/map.xmsgs
ad9226_verilog/_xmsgs/ngdbuild.xmsgs
ad9226_verilog/_xmsgs/par.xmsgs
ad9226_verilog/_xmsgs/pn_parser.xmsgs
ad9226_verilog/_xmsgs/trce.xmsgs
ad9226_verilog/_xmsgs/xst.xmsgs
ad9226_verilog/ad9226_test.bgn
ad9226_verilog/ad9226_test.bit
ad9226_verilog/ad9226_test.bld
ad9226_verilog/ad9226_test.cmd_log
ad9226_verilog/ad9226_test.cpj
ad9226_verilog/ad9226_test.drc
ad9226_verilog/ad9226_test.gise
ad9226_verilog/ad9226_test.lso
ad9226_verilog/ad9226_test.ncd
ad9226_verilog/ad9226_test.ngc
ad9226_verilog/ad9226_test.ngd
ad9226_verilog/ad9226_test.ngr
ad9226_verilog/ad9226_test.pad
ad9226_verilog/ad9226_test.par
ad9226_verilog/ad9226_test.pcf
ad9226_verilog/ad9226_test.prj
ad9226_verilog/ad9226_test.ptwx
ad9226_verilog/ad9226_test.stx
ad9226_verilog/ad9226_test.syr
ad9226_verilog/ad9226_test.twr
ad9226_verilog/ad9226_test.twx
ad9226_verilog/ad9226_test.ucf
ad9226_verilog/ad9226_test.unroutes
ad9226_verilog/ad9226_test.ut
ad9226_verilog/ad9226_test.xise
ad9226_verilog/ad9226_test.xpi
ad9226_verilog/ad9226_test.xst
ad9226_verilog/ad9226_test_bitgen.xwbt
ad9226_verilog/ad9226_test_envsettings.html
ad9226_verilog/ad9226_test_guide.ncd
ad9226_verilog/ad9226_test_map.map
ad9226_verilog/ad9226_test_map.mrp
ad9226_verilog/ad9226_test_map.ncd
ad9226_verilog/ad9226_test_map.ngm
ad9226_verilog/ad9226_test_map.xrpt
ad9226_verilog/ad9226_test_ngdbuild.xrpt
ad9226_verilog/ad9226_test_pad.csv
ad9226_verilog/ad9226_test_pad.txt
ad9226_verilog/ad9226_test_par.xrpt
ad9226_verilog/ad9226_test_summary.html
ad9226_verilog/ad9226_test_summary.xml
ad9226_verilog/ad9226_test_usage.xml
ad9226_verilog/ad9226_test_xst.xrpt
ad9226_verilog/chipscope_icon.ngc
ad9226_verilog/chipscope_icon.v
ad9226_verilog/chipscope_ila.ngc
ad9226_verilog/chipscope_ila.v
ad9226_verilog/ipcore_dir/
ad9226_verilog/ipcore_dir/_xmsgs/
ad9226_verilog/ipcore_dir/_xmsgs/cg.xmsgs
ad9226_verilog/ipcore_dir/_xmsgs/pn_parser.xmsgs
ad9226_verilog/ipcore_dir/coregen.cgp
ad9226_verilog/ipcore_dir/coregen.log
ad9226_verilog/ipcore_dir/create_pll.tcl
ad9226_verilog/ipcore_dir/create_pll2.tcl
ad9226_verilog/ipcore_dir/edit_pll.tcl
ad9226_verilog/ipcore_dir/pll/
ad9226_verilog/ipcore_dir/pll/clk_wiz_v3_6_readme.txt
ad9226_verilog/ipcore_dir/pll/doc/
ad9226_verilog/ipcore_dir/pll/doc/clk_wiz_v3_6_readme.txt
ad9226_verilog/ipcore_dir/pll/doc/clk_wiz_v3_6_vinfo.html
ad9226_verilog/ipcore_dir/pll/doc/pg065_clk_wiz.pdf
ad9226_verilog/ipcore_dir/pll/example_design/
ad9226_verilog/ipcore_dir/pll/example_design/pll_exdes.ucf
ad9226_verilog/ipcore_dir/pll/example_design/pll_exdes.v
ad9226_verilog/ipcore_dir/pll/example_design/pll_exdes.xdc
ad9226_verilog/ipcore_dir/pll/implement/
ad9226_verilog/ipcore_dir/pll/implement/implement.bat
ad9226_verilog/ipcore_dir/pll/implement/implement.sh
ad9226_verilog/ipcore_dir/pll/implement/planAhead_ise.bat
ad9226_verilog/ipcore_dir/pll/implement/planAhead_ise.sh
ad9226_verilog/ipcore_dir/pll/implement/planAhead_ise.tcl
ad9226_verilog/ipcore_dir/pll/implement/planAhead_rdn.bat
ad9226_verilog/ipcore_dir/pll/implement/planAhead_rdn.sh
ad9226_verilog/ipcore_dir/pll/implement/planAhead_rdn.tcl
ad9226_verilog/ipcore_dir/pll/implement/xst.prj
ad9226_verilog/ipcore_dir/pll/implement/xst.scr
ad9226_verilog/ipcore_dir/pll/simulation/
ad9226_verilog/ipcore_dir/pll/simulation/functional/
ad9226_verilog/ipcore_dir/pll/simulation/functional/simcmds.tcl
ad9226_verilog/ipcore_dir/pll/simulation/functional/simulate_isim.bat
ad9226_verilog/ipcore_dir/pll/simulation/functional/simulate_isim.sh
ad9226_verilog/ipcore_dir/pll/simulation/functional/simulate_mti.bat
ad9226_verilog/ipcore_dir/pll/simulation/functional/simulate_mti.do
ad9226_verilog/ipcore_dir/pll/simulation/functional/simulate_mti.sh
ad9226_verilog/ipcore_dir/pll/simulation/functional/simulate_ncsim.sh
ad9226_verilog/ipcore_dir/pll/simulation/functional/simulate_vcs.sh
ad9226_verilog/ipcore_dir/pll/simulation/functional/ucli_commands.key
ad9226_verilog/ipcore_dir/pll/simulation/functional/vcs_session.tcl
ad9226_verilog/ipcore_dir/pll/simulation/functional/wave.do
ad9226_verilog/ipcore_dir/pll/simulation/functional/wave.sv
ad9226_verilog/ipcore_dir/pll/simulation/pll_tb.v
ad9226_verilog/ipcore_dir/pll/simulation/timing/
ad9226_verilog/ipcore_dir/pll/simulation/timing/pll_tb.v
ad9226_verilog/ipcore_dir/pll/simulation/timing/sdf_cmd_file
ad9226_verilog/ipcore_dir/pll/simulation/timing/simcmds.tcl
ad9226_verilog/ipcore_dir/pll/simulation/timing/simulate_isim.sh
ad9226_verilog/ipcore_dir/pll/simulation/timing/simulate_mti.bat
ad9226_verilog/ipcore_dir/pll/simulation/timing/simulate_mti.do
ad9226_verilog/ipcore_dir/pll/simulation/timing/simulate_mti.sh
ad9226_verilog/ipcore_dir/pll/simulation/timing/simulate_ncsim.sh
ad9226_verilog/ipcore_dir/pll/simulation/timing/simulate_vcs.sh
ad9226_verilog/ipcore_dir/pll/simulation/timing/ucli_commands.key
ad9226_verilog/ipcore_dir/pll/simulation/timing/vcs_session.tcl
ad9226_verilog/ipcore
ad9226_verilog/.Xil/
ad9226_verilog/AD_summary.html
ad9226_verilog/_ngo/
ad9226_verilog/_ngo/netlist.lst
ad9226_verilog/_xmsgs/
ad9226_verilog/_xmsgs/bitgen.xmsgs
ad9226_verilog/_xmsgs/map.xmsgs
ad9226_verilog/_xmsgs/ngdbuild.xmsgs
ad9226_verilog/_xmsgs/par.xmsgs
ad9226_verilog/_xmsgs/pn_parser.xmsgs
ad9226_verilog/_xmsgs/trce.xmsgs
ad9226_verilog/_xmsgs/xst.xmsgs
ad9226_verilog/ad9226_test.bgn
ad9226_verilog/ad9226_test.bit
ad9226_verilog/ad9226_test.bld
ad9226_verilog/ad9226_test.cmd_log
ad9226_verilog/ad9226_test.cpj
ad9226_verilog/ad9226_test.drc
ad9226_verilog/ad9226_test.gise
ad9226_verilog/ad9226_test.lso
ad9226_verilog/ad9226_test.ncd
ad9226_verilog/ad9226_test.ngc
ad9226_verilog/ad9226_test.ngd
ad9226_verilog/ad9226_test.ngr
ad9226_verilog/ad9226_test.pad
ad9226_verilog/ad9226_test.par
ad9226_verilog/ad9226_test.pcf
ad9226_verilog/ad9226_test.prj
ad9226_verilog/ad9226_test.ptwx
ad9226_verilog/ad9226_test.stx
ad9226_verilog/ad9226_test.syr
ad9226_verilog/ad9226_test.twr
ad9226_verilog/ad9226_test.twx
ad9226_verilog/ad9226_test.ucf
ad9226_verilog/ad9226_test.unroutes
ad9226_verilog/ad9226_test.ut
ad9226_verilog/ad9226_test.xise
ad9226_verilog/ad9226_test.xpi
ad9226_verilog/ad9226_test.xst
ad9226_verilog/ad9226_test_bitgen.xwbt
ad9226_verilog/ad9226_test_envsettings.html
ad9226_verilog/ad9226_test_guide.ncd
ad9226_verilog/ad9226_test_map.map
ad9226_verilog/ad9226_test_map.mrp
ad9226_verilog/ad9226_test_map.ncd
ad9226_verilog/ad9226_test_map.ngm
ad9226_verilog/ad9226_test_map.xrpt
ad9226_verilog/ad9226_test_ngdbuild.xrpt
ad9226_verilog/ad9226_test_pad.csv
ad9226_verilog/ad9226_test_pad.txt
ad9226_verilog/ad9226_test_par.xrpt
ad9226_verilog/ad9226_test_summary.html
ad9226_verilog/ad9226_test_summary.xml
ad9226_verilog/ad9226_test_usage.xml
ad9226_verilog/ad9226_test_xst.xrpt
ad9226_verilog/chipscope_icon.ngc
ad9226_verilog/chipscope_icon.v
ad9226_verilog/chipscope_ila.ngc
ad9226_verilog/chipscope_ila.v
ad9226_verilog/ipcore_dir/
ad9226_verilog/ipcore_dir/_xmsgs/
ad9226_verilog/ipcore_dir/_xmsgs/cg.xmsgs
ad9226_verilog/ipcore_dir/_xmsgs/pn_parser.xmsgs
ad9226_verilog/ipcore_dir/coregen.cgp
ad9226_verilog/ipcore_dir/coregen.log
ad9226_verilog/ipcore_dir/create_pll.tcl
ad9226_verilog/ipcore_dir/create_pll2.tcl
ad9226_verilog/ipcore_dir/edit_pll.tcl
ad9226_verilog/ipcore_dir/pll/
ad9226_verilog/ipcore_dir/pll/clk_wiz_v3_6_readme.txt
ad9226_verilog/ipcore_dir/pll/doc/
ad9226_verilog/ipcore_dir/pll/doc/clk_wiz_v3_6_readme.txt
ad9226_verilog/ipcore_dir/pll/doc/clk_wiz_v3_6_vinfo.html
ad9226_verilog/ipcore_dir/pll/doc/pg065_clk_wiz.pdf
ad9226_verilog/ipcore_dir/pll/example_design/
ad9226_verilog/ipcore_dir/pll/example_design/pll_exdes.ucf
ad9226_verilog/ipcore_dir/pll/example_design/pll_exdes.v
ad9226_verilog/ipcore_dir/pll/example_design/pll_exdes.xdc
ad9226_verilog/ipcore_dir/pll/implement/
ad9226_verilog/ipcore_dir/pll/implement/implement.bat
ad9226_verilog/ipcore_dir/pll/implement/implement.sh
ad9226_verilog/ipcore_dir/pll/implement/planAhead_ise.bat
ad9226_verilog/ipcore_dir/pll/implement/planAhead_ise.sh
ad9226_verilog/ipcore_dir/pll/implement/planAhead_ise.tcl
ad9226_verilog/ipcore_dir/pll/implement/planAhead_rdn.bat
ad9226_verilog/ipcore_dir/pll/implement/planAhead_rdn.sh
ad9226_verilog/ipcore_dir/pll/implement/planAhead_rdn.tcl
ad9226_verilog/ipcore_dir/pll/implement/xst.prj
ad9226_verilog/ipcore_dir/pll/implement/xst.scr
ad9226_verilog/ipcore_dir/pll/simulation/
ad9226_verilog/ipcore_dir/pll/simulation/functional/
ad9226_verilog/ipcore_dir/pll/simulation/functional/simcmds.tcl
ad9226_verilog/ipcore_dir/pll/simulation/functional/simulate_isim.bat
ad9226_verilog/ipcore_dir/pll/simulation/functional/simulate_isim.sh
ad9226_verilog/ipcore_dir/pll/simulation/functional/simulate_mti.bat
ad9226_verilog/ipcore_dir/pll/simulation/functional/simulate_mti.do
ad9226_verilog/ipcore_dir/pll/simulation/functional/simulate_mti.sh
ad9226_verilog/ipcore_dir/pll/simulation/functional/simulate_ncsim.sh
ad9226_verilog/ipcore_dir/pll/simulation/functional/simulate_vcs.sh
ad9226_verilog/ipcore_dir/pll/simulation/functional/ucli_commands.key
ad9226_verilog/ipcore_dir/pll/simulation/functional/vcs_session.tcl
ad9226_verilog/ipcore_dir/pll/simulation/functional/wave.do
ad9226_verilog/ipcore_dir/pll/simulation/functional/wave.sv
ad9226_verilog/ipcore_dir/pll/simulation/pll_tb.v
ad9226_verilog/ipcore_dir/pll/simulation/timing/
ad9226_verilog/ipcore_dir/pll/simulation/timing/pll_tb.v
ad9226_verilog/ipcore_dir/pll/simulation/timing/sdf_cmd_file
ad9226_verilog/ipcore_dir/pll/simulation/timing/simcmds.tcl
ad9226_verilog/ipcore_dir/pll/simulation/timing/simulate_isim.sh
ad9226_verilog/ipcore_dir/pll/simulation/timing/simulate_mti.bat
ad9226_verilog/ipcore_dir/pll/simulation/timing/simulate_mti.do
ad9226_verilog/ipcore_dir/pll/simulation/timing/simulate_mti.sh
ad9226_verilog/ipcore_dir/pll/simulation/timing/simulate_ncsim.sh
ad9226_verilog/ipcore_dir/pll/simulation/timing/simulate_vcs.sh
ad9226_verilog/ipcore_dir/pll/simulation/timing/ucli_commands.key
ad9226_verilog/ipcore_dir/pll/simulation/timing/vcs_session.tcl
ad9226_verilog/ipcore
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