文件名称:uart16550_latest.tar
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- 上传时间:2017-02-16
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文件大小:1.47mb
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UART16550是16550兼容的UART核心(主要)。
总线接口是WISHBONE SoC总线启。B.
所有功能的标准选择16550 UART:FIFO的基础操作,要求和其他中断。
数据表可以下载从CVS树随着源代码-uart16550 is a 16550 compatible (mostly) UART core.
The bus interface is WISHBONE SoC bus Rev. B.
Features all the standard options of the 16550 UART: FIFO based operation, interrupt requests and other.
The datasheet can be downloaded the CVS tree along with the source code
总线接口是WISHBONE SoC总线启。B.
所有功能的标准选择16550 UART:FIFO的基础操作,要求和其他中断。
数据表可以下载从CVS树随着源代码-uart16550 is a 16550 compatible (mostly) UART core.
The bus interface is WISHBONE SoC bus Rev. B.
Features all the standard options of the 16550 UART: FIFO based operation, interrupt requests and other.
The datasheet can be downloaded the CVS tree along with the source code
(系统自动生成,下载前可以参看下载内容)
下载文件列表
uart16550/
uart16550/tags/
uart16550/tags/initial/
uart16550/tags/initial/verilog/
uart16550/tags/initial/verilog/timescale.v
uart16550/tags/initial/verilog/UART_defines.v
uart16550/tags/initial/verilog/UART_FIFO_t.v
uart16550/tags/initial/verilog/FIFO_inc.v
uart16550/tags/initial/verilog/UART_top.v
uart16550/tags/initial/verilog/UART_RX_FIFO.v
uart16550/tags/initial/verilog/UART_wb.v
uart16550/tags/initial/verilog/UART_TX_FIFO.v
uart16550/tags/initial/verilog/UART_regs.v
uart16550/tags/initial/verilog/UART_test.v
uart16550/tags/initial/verilog/ToDo.txt
uart16550/tags/initial/verilog/UART_FIFO.v
uart16550/tags/initial/Doc/
uart16550/tags/initial/Doc/UART_spec.pdf
uart16550/tags/rel_3/
uart16550/tags/rel_3/doc/
uart16550/tags/rel_3/doc/UART_spec.pdf
uart16550/tags/rel_3/doc/CHANGES.txt
uart16550/tags/rel_3/doc/src/
uart16550/tags/rel_3/doc/src/UART_spec.doc
uart16550/tags/rel_3/lint/
uart16550/tags/rel_3/lint/run/
uart16550/tags/rel_3/lint/run/.keepme
uart16550/tags/rel_3/lint/bin/
uart16550/tags/rel_3/lint/bin/.keepme
uart16550/tags/rel_3/lint/log/
uart16550/tags/rel_3/lint/log/.keepme
uart16550/tags/rel_3/lint/out/
uart16550/tags/rel_3/lint/out/.keepme
uart16550/tags/rel_3/sim/
uart16550/tags/rel_3/sim/rtl_sim/
uart16550/tags/rel_3/sim/rtl_sim/run/
uart16550/tags/rel_3/sim/rtl_sim/run/run_sim
uart16550/tags/rel_3/sim/rtl_sim/run/run_signalscan
uart16550/tags/rel_3/sim/rtl_sim/run/run_sim.scr
uart16550/tags/rel_3/sim/rtl_sim/bin/
uart16550/tags/rel_3/sim/rtl_sim/bin/sim.tcl
uart16550/tags/rel_3/sim/rtl_sim/bin/nc.scr
uart16550/tags/rel_3/sim/rtl_sim/log/
uart16550/tags/rel_3/sim/rtl_sim/log/.keepme
uart16550/tags/rel_3/sim/rtl_sim/log/uart_interrupts_report.log
uart16550/tags/rel_3/sim/rtl_sim/log/uart_interrupts_verbose.log
uart16550/tags/rel_3/sim/rtl_sim/src/
uart16550/tags/rel_3/sim/rtl_sim/src/.keepme
uart16550/tags/rel_3/sim/rtl_sim/out/
uart16550/tags/rel_3/sim/rtl_sim/out/.keepme
uart16550/tags/rel_3/sim/gate_sim/
uart16550/tags/rel_3/sim/gate_sim/run/
uart16550/tags/rel_3/sim/gate_sim/run/.keepme
uart16550/tags/rel_3/sim/gate_sim/bin/
uart16550/tags/rel_3/sim/gate_sim/bin/.keepme
uart16550/tags/rel_3/sim/gate_sim/log/
uart16550/tags/rel_3/sim/gate_sim/log/.keepme
uart16550/tags/rel_3/sim/gate_sim/src/
uart16550/tags/rel_3/sim/gate_sim/src/.keepme
uart16550/tags/rel_3/sim/gate_sim/out/
uart16550/tags/rel_3/sim/gate_sim/out/.keepme
uart16550/tags/rel_3/bench/
uart16550/tags/rel_3/bench/verilog/
uart16550/tags/rel_3/bench/verilog/uart_device.v
uart16550/tags/rel_3/bench/verilog/uart_testbench_utilities.v
uart16550/tags/rel_3/bench/verilog/uart_testbench_defines.v
uart16550/tags/rel_3/bench/verilog/test_cases/
uart16550/tags/rel_3/bench/verilog/test_cases/uart_int.v
uart16550/tags/rel_3/bench/verilog/uart_testbench.v
uart16550/tags/rel_3/bench/verilog/uart_test.v
uart16550/tags/rel_3/bench/verilog/uart_log.v
uart16550/tags/rel_3/bench/verilog/vapi.log
uart16550/tags/rel_3/bench/verilog/uart_wb_utilities.v
uart16550/tags/rel_3/bench/verilog/uart_device_utilities.v
uart16550/tags/rel_3/bench/verilog/wb_master_model.v
uart16550/tags/rel_3/bench/verilog/readme.txt
uart16550/tags/rel_3/bench/verilog/wb_model_defines.v
uart16550/tags/rel_3/bench/verilog/wb_mast.v
uart16550/tags/rel_3/bench/vhdl/
uart16550/tags/rel_3/bench/vhdl/.keepme
uart16550/tags/rel_3/syn/
uart16550/tags/rel_3/syn/run/
uart16550/tags/rel_3/syn/run/.keepme
uart16550/tags/rel_3/syn/bin/
uart16550/tags/rel_3/syn/bin/.keepme
uart16550/tags/rel_3/syn/log/
uart16550/tags/rel_3/syn/log/.keepme
uart16550/tags/rel_3/syn/src/
uart16550/tags/rel_3/syn/src/.keepme
uart16550/tags/rel_3/syn/out/
uart16550/tags/rel_3/syn/out/.keepme
uart16550/tags/rel_3/fv/
uart16550/tags/rel_3/fv/.keepme
uart16550/tags/rel_3/rtl/
uart16550/tags/rel_3/rtl/verilog/
uart16550/tags/rel_3/rtl/verilog/timescale.v
uart16550/tags/rel_3/rtl/verilog/uart_sync_flops.v
uart16550/tags/rel_3/rtl/verilog/uart_wb.v
uart16550/tags/rel_3/rtl/verilog/uart_regs.v
uart16550/tags/rel_3/rtl/verilog/uart_receiver.v
uart16550/tags/rel_3/rtl/verilog/uart_tfifo.v
uart16550/tags/rel_3/rtl/verilog/uart_defines.v
uart16550/tags/rel_3/rtl/verilog/uart_debug_if.v
uart16550/tags/rel_3/rtl/verilog/uart_transmitter.v
uart16550/tags/rel_3/rtl/verilog/uart_rfifo.v
uart16550/tags/rel_3/rtl/verilog/uart_top.v
uart16550/tags/rel_3/rtl/verilog/raminfr.v
uart16550/tags/rel_3/rtl/vhdl/
uart16550/tags/rel_3/rtl/vhdl/.keepme
uart16550/tags/rel_3/rtl/verilog-backup/
uart16550/tags/rel_3/rtl/verilog-backup/timescale.v
uart16550/tags/rel_3/rtl/verilog-backup/uart_wb.v
uart16550/tags/rel_3/rtl/verilog-backup/uart_regs.v
uart16550/tags/rel_3/rtl/verilog-backup/uart_receiver.v
uart16550/tags/rel_3/rtl/verilog-backup/uart_defines.v
uart16550/tags/rel_3/rtl/verilog-backup/uart_transmitter.v
uart16550/tags/rel_3/rtl/verilog-backup/uart_top.v
uart16550/tags/rel_3/rtl/verilog-backup/uart_fifo.v
uart16550/tags/NewFormat/
uart16550/tags/NewFormat/doc/
uart16550/tags/NewFormat/doc/UART_spec.pdf
uart16550/tags/NewFormat/doc/CHANGES.txt
uart16550/tags/NewFormat/doc/src/
uart16550/tags/NewFormat/doc/src/UART_spec.doc
uart16550/tags/NewFormat/sim/
uart16550/tags/
uart16550/tags/initial/
uart16550/tags/initial/verilog/
uart16550/tags/initial/verilog/timescale.v
uart16550/tags/initial/verilog/UART_defines.v
uart16550/tags/initial/verilog/UART_FIFO_t.v
uart16550/tags/initial/verilog/FIFO_inc.v
uart16550/tags/initial/verilog/UART_top.v
uart16550/tags/initial/verilog/UART_RX_FIFO.v
uart16550/tags/initial/verilog/UART_wb.v
uart16550/tags/initial/verilog/UART_TX_FIFO.v
uart16550/tags/initial/verilog/UART_regs.v
uart16550/tags/initial/verilog/UART_test.v
uart16550/tags/initial/verilog/ToDo.txt
uart16550/tags/initial/verilog/UART_FIFO.v
uart16550/tags/initial/Doc/
uart16550/tags/initial/Doc/UART_spec.pdf
uart16550/tags/rel_3/
uart16550/tags/rel_3/doc/
uart16550/tags/rel_3/doc/UART_spec.pdf
uart16550/tags/rel_3/doc/CHANGES.txt
uart16550/tags/rel_3/doc/src/
uart16550/tags/rel_3/doc/src/UART_spec.doc
uart16550/tags/rel_3/lint/
uart16550/tags/rel_3/lint/run/
uart16550/tags/rel_3/lint/run/.keepme
uart16550/tags/rel_3/lint/bin/
uart16550/tags/rel_3/lint/bin/.keepme
uart16550/tags/rel_3/lint/log/
uart16550/tags/rel_3/lint/log/.keepme
uart16550/tags/rel_3/lint/out/
uart16550/tags/rel_3/lint/out/.keepme
uart16550/tags/rel_3/sim/
uart16550/tags/rel_3/sim/rtl_sim/
uart16550/tags/rel_3/sim/rtl_sim/run/
uart16550/tags/rel_3/sim/rtl_sim/run/run_sim
uart16550/tags/rel_3/sim/rtl_sim/run/run_signalscan
uart16550/tags/rel_3/sim/rtl_sim/run/run_sim.scr
uart16550/tags/rel_3/sim/rtl_sim/bin/
uart16550/tags/rel_3/sim/rtl_sim/bin/sim.tcl
uart16550/tags/rel_3/sim/rtl_sim/bin/nc.scr
uart16550/tags/rel_3/sim/rtl_sim/log/
uart16550/tags/rel_3/sim/rtl_sim/log/.keepme
uart16550/tags/rel_3/sim/rtl_sim/log/uart_interrupts_report.log
uart16550/tags/rel_3/sim/rtl_sim/log/uart_interrupts_verbose.log
uart16550/tags/rel_3/sim/rtl_sim/src/
uart16550/tags/rel_3/sim/rtl_sim/src/.keepme
uart16550/tags/rel_3/sim/rtl_sim/out/
uart16550/tags/rel_3/sim/rtl_sim/out/.keepme
uart16550/tags/rel_3/sim/gate_sim/
uart16550/tags/rel_3/sim/gate_sim/run/
uart16550/tags/rel_3/sim/gate_sim/run/.keepme
uart16550/tags/rel_3/sim/gate_sim/bin/
uart16550/tags/rel_3/sim/gate_sim/bin/.keepme
uart16550/tags/rel_3/sim/gate_sim/log/
uart16550/tags/rel_3/sim/gate_sim/log/.keepme
uart16550/tags/rel_3/sim/gate_sim/src/
uart16550/tags/rel_3/sim/gate_sim/src/.keepme
uart16550/tags/rel_3/sim/gate_sim/out/
uart16550/tags/rel_3/sim/gate_sim/out/.keepme
uart16550/tags/rel_3/bench/
uart16550/tags/rel_3/bench/verilog/
uart16550/tags/rel_3/bench/verilog/uart_device.v
uart16550/tags/rel_3/bench/verilog/uart_testbench_utilities.v
uart16550/tags/rel_3/bench/verilog/uart_testbench_defines.v
uart16550/tags/rel_3/bench/verilog/test_cases/
uart16550/tags/rel_3/bench/verilog/test_cases/uart_int.v
uart16550/tags/rel_3/bench/verilog/uart_testbench.v
uart16550/tags/rel_3/bench/verilog/uart_test.v
uart16550/tags/rel_3/bench/verilog/uart_log.v
uart16550/tags/rel_3/bench/verilog/vapi.log
uart16550/tags/rel_3/bench/verilog/uart_wb_utilities.v
uart16550/tags/rel_3/bench/verilog/uart_device_utilities.v
uart16550/tags/rel_3/bench/verilog/wb_master_model.v
uart16550/tags/rel_3/bench/verilog/readme.txt
uart16550/tags/rel_3/bench/verilog/wb_model_defines.v
uart16550/tags/rel_3/bench/verilog/wb_mast.v
uart16550/tags/rel_3/bench/vhdl/
uart16550/tags/rel_3/bench/vhdl/.keepme
uart16550/tags/rel_3/syn/
uart16550/tags/rel_3/syn/run/
uart16550/tags/rel_3/syn/run/.keepme
uart16550/tags/rel_3/syn/bin/
uart16550/tags/rel_3/syn/bin/.keepme
uart16550/tags/rel_3/syn/log/
uart16550/tags/rel_3/syn/log/.keepme
uart16550/tags/rel_3/syn/src/
uart16550/tags/rel_3/syn/src/.keepme
uart16550/tags/rel_3/syn/out/
uart16550/tags/rel_3/syn/out/.keepme
uart16550/tags/rel_3/fv/
uart16550/tags/rel_3/fv/.keepme
uart16550/tags/rel_3/rtl/
uart16550/tags/rel_3/rtl/verilog/
uart16550/tags/rel_3/rtl/verilog/timescale.v
uart16550/tags/rel_3/rtl/verilog/uart_sync_flops.v
uart16550/tags/rel_3/rtl/verilog/uart_wb.v
uart16550/tags/rel_3/rtl/verilog/uart_regs.v
uart16550/tags/rel_3/rtl/verilog/uart_receiver.v
uart16550/tags/rel_3/rtl/verilog/uart_tfifo.v
uart16550/tags/rel_3/rtl/verilog/uart_defines.v
uart16550/tags/rel_3/rtl/verilog/uart_debug_if.v
uart16550/tags/rel_3/rtl/verilog/uart_transmitter.v
uart16550/tags/rel_3/rtl/verilog/uart_rfifo.v
uart16550/tags/rel_3/rtl/verilog/uart_top.v
uart16550/tags/rel_3/rtl/verilog/raminfr.v
uart16550/tags/rel_3/rtl/vhdl/
uart16550/tags/rel_3/rtl/vhdl/.keepme
uart16550/tags/rel_3/rtl/verilog-backup/
uart16550/tags/rel_3/rtl/verilog-backup/timescale.v
uart16550/tags/rel_3/rtl/verilog-backup/uart_wb.v
uart16550/tags/rel_3/rtl/verilog-backup/uart_regs.v
uart16550/tags/rel_3/rtl/verilog-backup/uart_receiver.v
uart16550/tags/rel_3/rtl/verilog-backup/uart_defines.v
uart16550/tags/rel_3/rtl/verilog-backup/uart_transmitter.v
uart16550/tags/rel_3/rtl/verilog-backup/uart_top.v
uart16550/tags/rel_3/rtl/verilog-backup/uart_fifo.v
uart16550/tags/NewFormat/
uart16550/tags/NewFormat/doc/
uart16550/tags/NewFormat/doc/UART_spec.pdf
uart16550/tags/NewFormat/doc/CHANGES.txt
uart16550/tags/NewFormat/doc/src/
uart16550/tags/NewFormat/doc/src/UART_spec.doc
uart16550/tags/NewFormat/sim/
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