文件名称:can_latest.tar
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控制器局域网或CAN是一个控制网络协议
博世在工业自动化和工业自动化中得到了广泛的应用
汽车行业。
大多数的专利可以由博世拥有，虽然有
没有限制在开发一个开源IP但可以为任何
从博世商用许可协议是一个不可或缺的先决条件。
尺寸大约12K门（930触发器）。-Controller Area Network or CAN is a control network protocol
Bosch that has found wide use in Industrial Automation and the
Automotive Industry.
Most of the patents of CAN are owned by Bosch and although there
are no restictions on developing an opensource CAN IP but for any
commercial use the protocol license Bosch is an indispensable prerequisite.
Size is approximately 12k gates (930 flip-flops).
博世在工业自动化和工业自动化中得到了广泛的应用
汽车行业。
大多数的专利可以由博世拥有，虽然有
没有限制在开发一个开源IP但可以为任何
从博世商用许可协议是一个不可或缺的先决条件。
尺寸大约12K门（930触发器）。-Controller Area Network or CAN is a control network protocol
Bosch that has found wide use in Industrial Automation and the
Automotive Industry.
Most of the patents of CAN are owned by Bosch and although there
are no restictions on developing an opensource CAN IP but for any
commercial use the protocol license Bosch is an indispensable prerequisite.
Size is approximately 12k gates (930 flip-flops).
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下载文件列表
can/
can/tags/
can/tags/branch-release-1-0/
can/tags/branch-release-1-0/syn/
can/tags/branch-release-1-0/syn/synplicity/
can/tags/branch-release-1-0/syn/synplicity/can.prj
can/tags/branch-release-1-0/syn/synplicity/rev_1/
can/tags/branch-release-1-0/syn/synplicity/rev_1/dir_keeper
can/tags/branch-release-1-0/syn/libero/
can/tags/branch-release-1-0/syn/libero/pinedit.gcf
can/tags/initial/
can/tags/initial/sim/
can/tags/initial/sim/rtl_sim/
can/tags/initial/sim/rtl_sim/run/
can/tags/initial/sim/rtl_sim/run/wave.do
can/tags/initial/sim/rtl_sim/run/clean
can/tags/initial/sim/rtl_sim/run/run_sim.scr
can/tags/initial/sim/rtl_sim/bin/
can/tags/initial/sim/rtl_sim/bin/hdl.var
can/tags/initial/sim/rtl_sim/bin/rtl_file_list
can/tags/initial/sim/rtl_sim/bin/cds.lib
can/tags/initial/sim/rtl_sim/bin/sim_file_list
can/tags/initial/sim/rtl_sim/log/
can/tags/initial/sim/rtl_sim/log/dir_keeper
can/tags/initial/sim/rtl_sim/out/
can/tags/initial/sim/rtl_sim/out/dir_keeper
can/tags/initial/bench/
can/tags/initial/bench/verilog/
can/tags/initial/bench/verilog/timescale.v
can/tags/initial/bench/verilog/can_testbench.v
can/tags/initial/rtl/
can/tags/initial/rtl/verilog/
can/tags/initial/rtl/verilog/can_bsp.v
can/tags/initial/rtl/verilog/can_register.v
can/tags/initial/rtl/verilog/can_registers.v
can/tags/initial/rtl/verilog/can_register_asyn_syn.v
can/tags/initial/rtl/verilog/can_defines.v
can/tags/initial/rtl/verilog/can_register_syn.v
can/tags/initial/rtl/verilog/can_bitstuff.v
can/tags/initial/rtl/verilog/can_register_asyn.v
can/tags/initial/rtl/verilog/can_btl.v
can/tags/initial/rtl/verilog/can_top.v
can/tags/rel_3/
can/tags/rel_3/rtl/
can/tags/rel_3/rtl/verilog/
can/tags/rel_3/rtl/verilog/can_bsp.v
can/tags/rel_3/rtl/verilog/can_register.v
can/tags/rel_3/rtl/verilog/can_ibo.v
can/tags/rel_3/rtl/verilog/can_registers.v
can/tags/rel_3/rtl/verilog/can_register_asyn_syn.v
can/tags/rel_3/rtl/verilog/can_defines.v
can/tags/rel_3/rtl/verilog/can_register_syn.v
can/tags/rel_3/rtl/verilog/can_fifo.v
can/tags/rel_3/rtl/verilog/can_acf.v
can/tags/rel_3/rtl/verilog/can_register_asyn.v
can/tags/rel_3/rtl/verilog/can_crc.v
can/tags/rel_3/rtl/verilog/can_btl.v
can/tags/rel_3/rtl/verilog/can_top.v
can/tags/rel_18/
can/tags/rel_18/sim/
can/tags/rel_18/sim/rtl_sim/
can/tags/rel_18/sim/rtl_sim/run/
can/tags/rel_18/sim/rtl_sim/run/wave.do
can/tags/rel_18/sim/rtl_sim/run/clean
can/tags/rel_18/sim/rtl_sim/run/run_sim.scr
can/tags/rel_18/sim/rtl_sim/bin/
can/tags/rel_18/sim/rtl_sim/bin/hdl.var
can/tags/rel_18/sim/rtl_sim/bin/rtl_file_list
can/tags/rel_18/sim/rtl_sim/bin/INCA_libs/
can/tags/rel_18/sim/rtl_sim/bin/INCA_libs/worklib/
can/tags/rel_18/sim/rtl_sim/bin/INCA_libs/worklib/dir_keeper
can/tags/rel_18/sim/rtl_sim/bin/cds.lib
can/tags/rel_18/sim/rtl_sim/bin/sim_file_list
can/tags/rel_18/sim/rtl_sim/bin/memory_file_list
can/tags/rel_18/sim/rtl_sim/log/
can/tags/rel_18/sim/rtl_sim/log/dir_keeper
can/tags/rel_18/sim/rtl_sim/out/
can/tags/rel_18/sim/rtl_sim/out/dir_keeper
can/tags/rel_18/bench/
can/tags/rel_18/bench/verilog/
can/tags/rel_18/bench/verilog/timescale.v
can/tags/rel_18/bench/verilog/can_testbench.v
can/tags/rel_18/bench/verilog/can_testbench_defines.v
can/tags/rel_18/syn/
can/tags/rel_18/syn/synplicity/
can/tags/rel_18/syn/synplicity/can.prj
can/tags/rel_18/syn/synplicity/rev_1/
can/tags/rel_18/syn/synplicity/rev_1/dir_keeper
can/tags/rel_18/syn/libero/
can/tags/rel_18/syn/libero/pinedit.gcf
can/tags/rel_18/rtl/
can/tags/rel_18/rtl/verilog/
can/tags/rel_18/rtl/verilog/can_bsp.v
can/tags/rel_18/rtl/verilog/can_register.v
can/tags/rel_18/rtl/verilog/can_ibo.v
can/tags/rel_18/rtl/verilog/can_registers.v
can/tags/rel_18/rtl/verilog/can_register_asyn_syn.v
can/tags/rel_18/rtl/verilog/can_defines.v
can/tags/rel_18/rtl/verilog/can_register_syn.v
can/tags/rel_18/rtl/verilog/can_fifo.v
can/tags/rel_18/rtl/verilog/can_acf.v
can/tags/rel_18/rtl/verilog/can_register_asyn.v
can/tags/rel_18/rtl/verilog/can_crc.v
can/tags/rel_18/rtl/verilog/can_btl.v
can/tags/rel_18/rtl/verilog/can_top.v
can/tags/rel_15/
can/tags/rel_15/sim/
can/tags/rel_15/sim/rtl_sim/
can/tags/rel_15/sim/rtl_sim/run/
can/tags/rel_15/sim/rtl_sim/run/wave.do
can/tags/rel_15/sim/rtl_sim/run/clean
can/tags/rel_15/sim/rtl_sim/run/run_sim.scr
can/tags/rel_15/sim/rtl_sim/bin/
can/tags/rel_15/sim/rtl_sim/bin/hdl.var
can/tags/rel_15/sim/rtl_sim/bin/rtl_file_list
can/tags/rel_15/sim/rtl_sim/bin/INCA_libs/
can/tags/rel_15/sim/rtl_sim/bin/INCA_libs/worklib/
can/tags/rel_15/sim/rtl_sim/bin/INCA_libs/worklib/dir_keeper
can/tags/rel_15/sim/rtl_sim/bin/cds.lib
can/tags/rel_15/sim/rtl_sim/bin/sim_file_list
can/tags/rel_15/sim/rtl_sim/bin/memory_file_list
can/tags/rel_15/sim/rtl_sim/log/
can/tags/rel_15/sim/rtl_sim/log/dir_keeper
can/tags/rel_15/sim/rtl_sim/out/
can/tags/rel_15/sim/rtl_sim/out/dir_keeper
can/tags/rel_15/bench/
can/tags/rel_15/bench/verilog/
can/tags/rel_15/bench/verilog/timescale.v
can/tags/rel_15/bench/verilog/can_testbench.v
can/tags/rel_15/bench/verilog/can_testbench_defines.v
can/tags/rel_15/syn/
can/tags/rel_15/syn/synplicity/
can/tags/rel_15/syn/synplicity/can.prj
can/tags/rel_15/syn/synplicit
can/tags/
can/tags/branch-release-1-0/
can/tags/branch-release-1-0/syn/
can/tags/branch-release-1-0/syn/synplicity/
can/tags/branch-release-1-0/syn/synplicity/can.prj
can/tags/branch-release-1-0/syn/synplicity/rev_1/
can/tags/branch-release-1-0/syn/synplicity/rev_1/dir_keeper
can/tags/branch-release-1-0/syn/libero/
can/tags/branch-release-1-0/syn/libero/pinedit.gcf
can/tags/initial/
can/tags/initial/sim/
can/tags/initial/sim/rtl_sim/
can/tags/initial/sim/rtl_sim/run/
can/tags/initial/sim/rtl_sim/run/wave.do
can/tags/initial/sim/rtl_sim/run/clean
can/tags/initial/sim/rtl_sim/run/run_sim.scr
can/tags/initial/sim/rtl_sim/bin/
can/tags/initial/sim/rtl_sim/bin/hdl.var
can/tags/initial/sim/rtl_sim/bin/rtl_file_list
can/tags/initial/sim/rtl_sim/bin/cds.lib
can/tags/initial/sim/rtl_sim/bin/sim_file_list
can/tags/initial/sim/rtl_sim/log/
can/tags/initial/sim/rtl_sim/log/dir_keeper
can/tags/initial/sim/rtl_sim/out/
can/tags/initial/sim/rtl_sim/out/dir_keeper
can/tags/initial/bench/
can/tags/initial/bench/verilog/
can/tags/initial/bench/verilog/timescale.v
can/tags/initial/bench/verilog/can_testbench.v
can/tags/initial/rtl/
can/tags/initial/rtl/verilog/
can/tags/initial/rtl/verilog/can_bsp.v
can/tags/initial/rtl/verilog/can_register.v
can/tags/initial/rtl/verilog/can_registers.v
can/tags/initial/rtl/verilog/can_register_asyn_syn.v
can/tags/initial/rtl/verilog/can_defines.v
can/tags/initial/rtl/verilog/can_register_syn.v
can/tags/initial/rtl/verilog/can_bitstuff.v
can/tags/initial/rtl/verilog/can_register_asyn.v
can/tags/initial/rtl/verilog/can_btl.v
can/tags/initial/rtl/verilog/can_top.v
can/tags/rel_3/
can/tags/rel_3/rtl/
can/tags/rel_3/rtl/verilog/
can/tags/rel_3/rtl/verilog/can_bsp.v
can/tags/rel_3/rtl/verilog/can_register.v
can/tags/rel_3/rtl/verilog/can_ibo.v
can/tags/rel_3/rtl/verilog/can_registers.v
can/tags/rel_3/rtl/verilog/can_register_asyn_syn.v
can/tags/rel_3/rtl/verilog/can_defines.v
can/tags/rel_3/rtl/verilog/can_register_syn.v
can/tags/rel_3/rtl/verilog/can_fifo.v
can/tags/rel_3/rtl/verilog/can_acf.v
can/tags/rel_3/rtl/verilog/can_register_asyn.v
can/tags/rel_3/rtl/verilog/can_crc.v
can/tags/rel_3/rtl/verilog/can_btl.v
can/tags/rel_3/rtl/verilog/can_top.v
can/tags/rel_18/
can/tags/rel_18/sim/
can/tags/rel_18/sim/rtl_sim/
can/tags/rel_18/sim/rtl_sim/run/
can/tags/rel_18/sim/rtl_sim/run/wave.do
can/tags/rel_18/sim/rtl_sim/run/clean
can/tags/rel_18/sim/rtl_sim/run/run_sim.scr
can/tags/rel_18/sim/rtl_sim/bin/
can/tags/rel_18/sim/rtl_sim/bin/hdl.var
can/tags/rel_18/sim/rtl_sim/bin/rtl_file_list
can/tags/rel_18/sim/rtl_sim/bin/INCA_libs/
can/tags/rel_18/sim/rtl_sim/bin/INCA_libs/worklib/
can/tags/rel_18/sim/rtl_sim/bin/INCA_libs/worklib/dir_keeper
can/tags/rel_18/sim/rtl_sim/bin/cds.lib
can/tags/rel_18/sim/rtl_sim/bin/sim_file_list
can/tags/rel_18/sim/rtl_sim/bin/memory_file_list
can/tags/rel_18/sim/rtl_sim/log/
can/tags/rel_18/sim/rtl_sim/log/dir_keeper
can/tags/rel_18/sim/rtl_sim/out/
can/tags/rel_18/sim/rtl_sim/out/dir_keeper
can/tags/rel_18/bench/
can/tags/rel_18/bench/verilog/
can/tags/rel_18/bench/verilog/timescale.v
can/tags/rel_18/bench/verilog/can_testbench.v
can/tags/rel_18/bench/verilog/can_testbench_defines.v
can/tags/rel_18/syn/
can/tags/rel_18/syn/synplicity/
can/tags/rel_18/syn/synplicity/can.prj
can/tags/rel_18/syn/synplicity/rev_1/
can/tags/rel_18/syn/synplicity/rev_1/dir_keeper
can/tags/rel_18/syn/libero/
can/tags/rel_18/syn/libero/pinedit.gcf
can/tags/rel_18/rtl/
can/tags/rel_18/rtl/verilog/
can/tags/rel_18/rtl/verilog/can_bsp.v
can/tags/rel_18/rtl/verilog/can_register.v
can/tags/rel_18/rtl/verilog/can_ibo.v
can/tags/rel_18/rtl/verilog/can_registers.v
can/tags/rel_18/rtl/verilog/can_register_asyn_syn.v
can/tags/rel_18/rtl/verilog/can_defines.v
can/tags/rel_18/rtl/verilog/can_register_syn.v
can/tags/rel_18/rtl/verilog/can_fifo.v
can/tags/rel_18/rtl/verilog/can_acf.v
can/tags/rel_18/rtl/verilog/can_register_asyn.v
can/tags/rel_18/rtl/verilog/can_crc.v
can/tags/rel_18/rtl/verilog/can_btl.v
can/tags/rel_18/rtl/verilog/can_top.v
can/tags/rel_15/
can/tags/rel_15/sim/
can/tags/rel_15/sim/rtl_sim/
can/tags/rel_15/sim/rtl_sim/run/
can/tags/rel_15/sim/rtl_sim/run/wave.do
can/tags/rel_15/sim/rtl_sim/run/clean
can/tags/rel_15/sim/rtl_sim/run/run_sim.scr
can/tags/rel_15/sim/rtl_sim/bin/
can/tags/rel_15/sim/rtl_sim/bin/hdl.var
can/tags/rel_15/sim/rtl_sim/bin/rtl_file_list
can/tags/rel_15/sim/rtl_sim/bin/INCA_libs/
can/tags/rel_15/sim/rtl_sim/bin/INCA_libs/worklib/
can/tags/rel_15/sim/rtl_sim/bin/INCA_libs/worklib/dir_keeper
can/tags/rel_15/sim/rtl_sim/bin/cds.lib
can/tags/rel_15/sim/rtl_sim/bin/sim_file_list
can/tags/rel_15/sim/rtl_sim/bin/memory_file_list
can/tags/rel_15/sim/rtl_sim/log/
can/tags/rel_15/sim/rtl_sim/log/dir_keeper
can/tags/rel_15/sim/rtl_sim/out/
can/tags/rel_15/sim/rtl_sim/out/dir_keeper
can/tags/rel_15/bench/
can/tags/rel_15/bench/verilog/
can/tags/rel_15/bench/verilog/timescale.v
can/tags/rel_15/bench/verilog/can_testbench.v
can/tags/rel_15/bench/verilog/can_testbench_defines.v
can/tags/rel_15/syn/
can/tags/rel_15/syn/synplicity/
can/tags/rel_15/syn/synplicity/can.prj
can/tags/rel_15/syn/synplicit
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