文件名称:spi_verilog_master_slave_latest.tar
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- 上传时间：2017-02-21
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该项目从需要具有强大而简单的以VHDL编写的SPI接口核心开始，用于通用的FPGA到设备接口。
所产生的内核产生小而高效的电路，从非常慢的SPI时钟到超过50MHz的SPI时钟。-This project started the need to have robust yet simple SPI interface cores written in VHDL to use in generic FPGA-to-device interfacing.
The resulting cores generate small and efficient circuits, that operate very slow SPI clocks up to over 50MHz SPI clocks.
所产生的内核产生小而高效的电路，从非常慢的SPI时钟到超过50MHz的SPI时钟。-This project started the need to have robust yet simple SPI interface cores written in VHDL to use in generic FPGA-to-device interfacing.
The resulting cores generate small and efficient circuits, that operate very slow SPI clocks up to over 50MHz SPI clocks.
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下载文件列表
spi_verilog_master_slave/
spi_verilog_master_slave/tags/
spi_verilog_master_slave/branches/
spi_verilog_master_slave/branches/branches/
spi_verilog_master_slave/trunk/
spi_verilog_master_slave/trunk/testbench/
spi_verilog_master_slave/trunk/testbench/TB_SPI_MasSlv.v
spi_verilog_master_slave/trunk/rtl/
spi_verilog_master_slave/trunk/rtl/spi_slave.v
spi_verilog_master_slave/trunk/rtl/spi_master.v
spi_verilog_master_slave/tags/
spi_verilog_master_slave/branches/
spi_verilog_master_slave/branches/branches/
spi_verilog_master_slave/trunk/
spi_verilog_master_slave/trunk/testbench/
spi_verilog_master_slave/trunk/testbench/TB_SPI_MasSlv.v
spi_verilog_master_slave/trunk/rtl/
spi_verilog_master_slave/trunk/rtl/spi_slave.v
spi_verilog_master_slave/trunk/rtl/spi_master.v
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