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文件名称:DDR_TEST

  • 所属分类：
    VHDL-FPGA-Verilog
  • 标签属性：
    [PDF]
  • 上传时间：
    2017-02-25
  • 文件大小：
    6.58mb
  • 已下载：
    0次
  • 提 供 者：
    陈****
  • 相关连接：
    无
  • 下载说明：
    别用迅雷下载，失败请重下，重下不扣分！
修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

基于xc65slx16的ise 14.7 DDR3测试模版，经过验证，可供fpga开发参考学习，也可作为开发模版。-Based on xc65slx16 ise 14.7 DDR3 test template, validated and can be used for reference in the fpga development study, also can be used as a template development.
(系统自动生成,下载前可以参看下载内容)

下载文件列表

DDR_TEST/MIG_PRG/DOC/SPARTAN6 MCB MIG Core生成.doc
DDR_TEST/MIG_PRG/DOC/ug388.pdf
DDR_TEST/MIG_PRG/DOC/ug416.pdf
DDR_TEST/MIG_PRG/MIG_RPG/mig.prj
DDR_TEST/MIG_PRG/MIG_RPG/mis603/docs/ug388.pdf
DDR_TEST/MIG_PRG/MIG_RPG/mis603/docs/ug416.pdf
DDR_TEST/MIG_PRG/MIG_RPG/mis603/example_design/datasheet.txt
DDR_TEST/MIG_PRG/MIG_RPG/mis603/example_design/log.txt
DDR_TEST/MIG_PRG/MIG_RPG/mis603/example_design/mig.prj
DDR_TEST/MIG_PRG/MIG_RPG/mis603/example_design/par/create_ise.bat
DDR_TEST/MIG_PRG/MIG_RPG/mis603/example_design/par/example_top.ucf
DDR_TEST/MIG_PRG/MIG_RPG/mis603/example_design/par/icon_coregen.xco
DDR_TEST/MIG_PRG/MIG_RPG/mis603/example_design/par/ila_coregen.xco
DDR_TEST/MIG_PRG/MIG_RPG/mis603/example_design/par/ise_flow.bat
DDR_TEST/MIG_PRG/MIG_RPG/mis603/example_design/par/ise_run.txt
DDR_TEST/MIG_PRG/MIG_RPG/mis603/example_design/par/makeproj.bat
DDR_TEST/MIG_PRG/MIG_RPG/mis603/example_design/par/mem_interface_top.ut
DDR_TEST/MIG_PRG/MIG_RPG/mis603/example_design/par/readme.txt
DDR_TEST/MIG_PRG/MIG_RPG/mis603/example_design/par/rem_files.bat
DDR_TEST/MIG_PRG/MIG_RPG/mis603/example_design/par/set_ise_prop.tcl
DDR_TEST/MIG_PRG/MIG_RPG/mis603/example_design/par/vio_coregen.xco
DDR_TEST/MIG_PRG/MIG_RPG/mis603/example_design/rtl/example_top.v
DDR_TEST/MIG_PRG/MIG_RPG/mis603/example_design/rtl/infrastructure.v
DDR_TEST/MIG_PRG/MIG_RPG/mis603/example_design/rtl/mcb_controller/iodrp_controller.v
DDR_TEST/MIG_PRG/MIG_RPG/mis603/example_design/rtl/mcb_controller/iodrp_mcb_controller.v
DDR_TEST/MIG_PRG/MIG_RPG/mis603/example_design/rtl/mcb_controller/mcb_raw_wrapper.v
DDR_TEST/MIG_PRG/MIG_RPG/mis603/example_design/rtl/mcb_controller/mcb_soft_calibration.v
DDR_TEST/MIG_PRG/MIG_RPG/mis603/example_design/rtl/mcb_controller/mcb_soft_calibration_top.v
DDR_TEST/MIG_PRG/MIG_RPG/mis603/example_design/rtl/mcb_controller/mcb_ui_top.v
DDR_TEST/MIG_PRG/MIG_RPG/mis603/example_design/rtl/memc_tb_top.v
DDR_TEST/MIG_PRG/MIG_RPG/mis603/example_design/rtl/memc_wrapper.v
DDR_TEST/MIG_PRG/MIG_RPG/mis603/example_design/rtl/traffic_gen/afifo.v
DDR_TEST/MIG_PRG/MIG_RPG/mis603/example_design/rtl/traffic_gen/cmd_gen.v
DDR_TEST/MIG_PRG/MIG_RPG/mis603/example_design/rtl/traffic_gen/cmd_prbs_gen.v
DDR_TEST/MIG_PRG/MIG_RPG/mis603/example_design/rtl/traffic_gen/data_prbs_gen.v
DDR_TEST/MIG_PRG/MIG_RPG/mis603/example_design/rtl/traffic_gen/init_mem_pattern_ctr.v
DDR_TEST/MIG_PRG/MIG_RPG/mis603/example_design/rtl/traffic_gen/mcb_flow_control.v
DDR_TEST/MIG_PRG/MIG_RPG/mis603/example_design/rtl/traffic_gen/mcb_traffic_gen.v
DDR_TEST/MIG_PRG/MIG_RPG/mis603/example_design/rtl/traffic_gen/rd_data_gen.v
DDR_TEST/MIG_PRG/MIG_RPG/mis603/example_design/rtl/traffic_gen/read_data_path.v
DDR_TEST/MIG_PRG/MIG_RPG/mis603/example_design/rtl/traffic_gen/read_posted_fifo.v
DDR_TEST/MIG_PRG/MIG_RPG/mis603/example_design/rtl/traffic_gen/sp6_data_gen.v
DDR_TEST/MIG_PRG/MIG_RPG/mis603/example_design/rtl/traffic_gen/tg_status.v
DDR_TEST/MIG_PRG/MIG_RPG/mis603/example_design/rtl/traffic_gen/v6_data_gen.v
DDR_TEST/MIG_PRG/MIG_RPG/mis603/example_design/rtl/traffic_gen/write_data_path.v
DDR_TEST/MIG_PRG/MIG_RPG/mis603/example_design/rtl/traffic_gen/wr_data_gen.v
DDR_TEST/MIG_PRG/MIG_RPG/mis603/example_design/sim/functional/ddr3_model_c3.v
DDR_TEST/MIG_PRG/MIG_RPG/mis603/example_design/sim/functional/ddr3_model_parameters_c3.vh
DDR_TEST/MIG_PRG/MIG_RPG/mis603/example_design/sim/functional/isim.bat
DDR_TEST/MIG_PRG/MIG_RPG/mis603/example_design/sim/functional/isim.tcl
DDR_TEST/MIG_PRG/MIG_RPG/mis603/example_design/sim/functional/mis603.prj
DDR_TEST/MIG_PRG/MIG_RPG/mis603/example_design/sim/functional/readme.txt
DDR_TEST/MIG_PRG/MIG_RPG/mis603/example_design/sim/functional/sim.do
DDR_TEST/MIG_PRG/MIG_RPG/mis603/example_design/sim/functional/sim_tb_top.v
DDR_TEST/MIG_PRG/MIG_RPG/mis603/example_design/synth/example_top.lso
DDR_TEST/MIG_PRG/MIG_RPG/mis603/example_design/synth/example_top.prj
DDR_TEST/MIG_PRG/MIG_RPG/mis603/example_design/synth/mem_interface_top_synp.sdc
DDR_TEST/MIG_PRG/MIG_RPG/mis603/example_design/synth/script_synp.tcl
DDR_TEST/MIG_PRG/MIG_RPG/mis603/user_design/datasheet.txt
DDR_TEST/MIG_PRG/MIG_RPG/mis603/user_design/log.txt
DDR_TEST/MIG_PRG/MIG_RPG/mis603/user_design/mig.prj
DDR_TEST/MIG_PRG/MIG_RPG/mis603/user_design/par/create_ise.bat
DDR_TEST/MIG_PRG/MIG_RPG/mis603/user_design/par/icon_coregen.xco
DDR_TEST/MIG_PRG/MIG_RPG/mis603/user_design/par/ila_coregen.xco
DDR_TEST/MIG_PRG/MIG_RPG/mis603/user_design/par/ise_flow.bat
DDR_TEST/MIG_PRG/MIG_RPG/mis603/user_design/par/ise_run.txt
DDR_TEST/MIG_PRG/MIG_RPG/mis603/user_design/par/makeproj.bat
DDR_TEST/MIG_PRG/MIG_RPG/mis603/user_design/par/mem_interface_top.ut
DDR_TEST/MIG_PRG/MIG_RPG/mis603/user_design/par/mis603.ucf
DDR_TEST/MIG_PRG/MIG_RPG/mis603/user_design/par/readme.txt
DDR_TEST/MIG_PRG/MIG_RPG/mis603/user_design/par/rem_files.bat
DDR_TEST/MIG_PRG/MIG_RPG/mis603/user_design/par/set_ise_prop.tcl
DDR_TEST/MIG_PRG/MIG_RPG/mis603/user_design/par/vio_coregen.xco
DDR_TEST/MIG_PRG/MIG_RPG/mis603/user_design/rtl/infrastructure.v
DDR_TEST/MIG_PRG/MIG_RPG/mis603/user_design/rtl/mcb_controller/iodrp_controller.v
DDR_TEST/M

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