discrete_time_pll/compile_and_launch.tcl
discrete_time_pll/cosim_cmds.m
discrete_time_pll/discrete_pll_1.mdl
discrete_time_pll/discrete_pll_10.mdl
discrete_time_pll/discrete_pll_10.mdl.r2014b
discrete_time_pll/discrete_pll_11.mdl
discrete_time_pll/discrete_pll_3.mdl
discrete_time_pll/discrete_pll_5.mdl
discrete_time_pll/discrete_pll_7.mdl
discrete_time_pll/discrete_pll_8.mdl
discrete_time_pll/discrete_pll_9a.mdl
discrete_time_pll/DT_complex_pll_init.m
discrete_time_pll/dt_pll.m
discrete_time_pll/DT_pll_init.m
discrete_time_pll/dt_pll_sel.txt
discrete_time_pll/example_sel2html.m
discrete_time_pll/hdlsrc/discrete_pll_10/Carrier_Recovery_PLL.v
discrete_time_pll/hdlsrc/discrete_pll_10/Carrier_Recovery_PLL.vhd
discrete_time_pll/hdlsrc/discrete_pll_10/Carrier_Recovery_PLL_compile.do
discrete_time_pll/hdlsrc/discrete_pll_10/Carrier_Recovery_PLL_map.txt
discrete_time_pll/hdlsrc/discrete_pll_10/Carrier_Recovery_PLL_report.html
discrete_time_pll/hdlsrc/discrete_pll_10/discrete_pll_10_report.html
discrete_time_pll/hdlsrc/discrete_pll_10/Extended_Costas_Phase_Detector_2.v
discrete_time_pll/hdlsrc/discrete_pll_10/Extended_Costas_Phase_Detector_2.vhd
discrete_time_pll/hdlsrc/discrete_pll_10/gm_discrete_pll_10.slx
discrete_time_pll/hdlsrc/discrete_pll_10/hdlcodegenstatus.mat
discrete_time_pll/hdlsrc/discrete_pll_10/P_I_Controller_2.v
discrete_time_pll/hdlsrc/discrete_pll_10/P_I_Controller_2.vhd
discrete_time_pll/hdlsrc/discrete_pll_10/Table_Lookup_NCO2.v
discrete_time_pll/hdlsrc/discrete_pll_10/Table_Lookup_NCO2.vhd
discrete_time_pll/hdlsrc/discrete_pll_10/vsim.wlf
discrete_time_pll/hdlsrc/work/_info
discrete_time_pll/transcript
pll_design_cp_v2/Bode_Plot.m
pll_design_cp_v2/CL_Bode_Plot.m
pll_design_cp_v2/comp_design_1.mat
pll_design_cp_v2/example_sel2html.m
pll_design_cp_v2/Exported_C_Design.mat
pll_design_cp_v2/linearize_model_1.m
pll_design_cp_v2/Loop_Compensator_Analysis.m
pll_design_cp_v2/Loop_Compensator_RC_SS_1.slx
pll_design_cp_v2/measured_phase_noise.mat
pll_design_cp_v2/phase_detector_gain_SS_1.slx
pll_design_cp_v2/pll.m
pll_design_cp_v2/pll_components_SS.slx
pll_design_cp_v2/pll_d1_g_and_p_margins_SS_a.slx
pll_design_cp_v2/pll_design.txt
pll_design_cp_v2/pll_design_loop_compensator_0.m
pll_design_cp_v2/pll_design_phase_noise_1.m
pll_design_cp_v2/PLL_Parameters_1.mat
pll_design_cp_v2/pll_pd_compensator_SS_0.slx
pll_design_cp_v2/pll_pd_optimizer_SS_6x.slx
pll_design_cp_v2/pll_pd_optimizer_SS_6x_sdosession.mat
pll_design_cp_v2/pll_pd_optimizer_SS_6x_sdosession_BACKUP.mat
pll_design_cp_v2/pll_pd_phase_noise_SS_1.slx
pll_design_cp_v2/pll_phase_and_time_domain_CL_Xfer_SS_1.slx
pll_design_cp_v2/pll_phase_and_time_domain_SS_2.slx
pll_design_cp_v2/pll_spectrum_SS_3.slx
pll_design_cp_v2/pll_spectrum_SS_4.slx
pll_design_cp_v2/pll_spectrum_SS_5.slx
pll_design_cp_v2/plot_dbc_per_hz.m
pll_design_cp_v2/Predicted_Phase_Noise.mat
pll_design_cp_v2/screen_caps.doc
pll_design_cp_v2/VCO_noise_profile_3.m
pll_behavioral_and_circuit_loop_compensators.slx
pll_d1_g_and_p_margins.slx
pll_ex.m
pll_examples.txt
pll_wbsd_2.mdl
quartz_resonator_control_SS_6.mdl
README.docx
simple_pll_3x.slx
VCO_noise_profile_3.m
vco_phase_noise_3.mdl
VCO_plot_dbc_per_hz.m
Bode_Plot.m
circuit_level_comp.png
cs_5.mdl
DFE_CDR_7.mdl
diff_backplane_model.mat
dm_pll_2.mdl
example_sel2html.m
fractional_4.mdl
MDLL_rab_1.mdl
license.txt