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文件名称:project_1

  • 所属分类：
    VHDL-FPGA-Verilog
  • 标签属性：
    [Linux] [SHELL] [源码]
  • 上传时间：
    2017-03-23
  • 文件大小：
    200.5kb
  • 已下载：
    0次
  • 提 供 者：
    Ta***
  • 相关连接：
    无
  • 下载说明：
    别用迅雷下载，失败请重下，重下不扣分！
修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

Creation of FPGA-based device. circuit represents a simple device, containing D Flip-Flop with optional asynchronous Reset inputs

and AND logic gate
(系统自动生成,下载前可以参看下载内容)

下载文件列表

project_1/
project_1/project_1.cache/
project_1/project_1.cache/compile_simlib/
project_1/project_1.cache/compile_simlib/activehdl/
project_1/project_1.cache/compile_simlib/ies/
project_1/project_1.cache/compile_simlib/modelsim/
project_1/project_1.cache/compile_simlib/questa/
project_1/project_1.cache/compile_simlib/riviera/
project_1/project_1.cache/compile_simlib/vcs/
project_1/project_1.cache/wt/
project_1/project_1.cache/wt/gui_resources.wdf
project_1/project_1.cache/wt/java_command_handlers.wdf
project_1/project_1.cache/wt/project.wpc
project_1/project_1.cache/wt/synthesis.wdf
project_1/project_1.cache/wt/synthesis_details.wdf
project_1/project_1.cache/wt/webtalk_pa.xml
project_1/project_1.cache/wt/xsim.wdf
project_1/project_1.hw/
project_1/project_1.hw/project_1.lpr
project_1/project_1.ip_user_files/
project_1/project_1.ip_user_files/bd/
project_1/project_1.ip_user_files/bd/schematic/
project_1/project_1.ip_user_files/bd/schematic/hdl/
project_1/project_1.ip_user_files/bd/schematic/hdl/schematic.vhd
project_1/project_1.ip_user_files/bd/schematic/ip/
project_1/project_1.ip_user_files/bd/schematic/ip/schematic_and_comp_0_0/
project_1/project_1.ip_user_files/bd/schematic/ip/schematic_and_comp_0_0/sim/
project_1/project_1.ip_user_files/bd/schematic/ip/schematic_and_comp_0_0/sim/schematic_and_comp_0_0.vhd
project_1/project_1.ip_user_files/bd/schematic/ip/schematic_fdc_comp_0_0/
project_1/project_1.ip_user_files/bd/schematic/ip/schematic_fdc_comp_0_0/sim/
project_1/project_1.ip_user_files/bd/schematic/ip/schematic_fdc_comp_0_0/sim/schematic_fdc_comp_0_0.vhd
project_1/project_1.ip_user_files/README.txt
project_1/project_1.ip_user_files/sim_scripts/
project_1/project_1.ip_user_files/sim_scripts/schematic/
project_1/project_1.ip_user_files/sim_scripts/schematic/activehdl/
project_1/project_1.ip_user_files/sim_scripts/schematic/activehdl/compile.do
project_1/project_1.ip_user_files/sim_scripts/schematic/activehdl/file_info.txt
project_1/project_1.ip_user_files/sim_scripts/schematic/activehdl/README.txt
project_1/project_1.ip_user_files/sim_scripts/schematic/activehdl/schematic.sh
project_1/project_1.ip_user_files/sim_scripts/schematic/activehdl/schematic.udo
project_1/project_1.ip_user_files/sim_scripts/schematic/activehdl/simulate.do
project_1/project_1.ip_user_files/sim_scripts/schematic/activehdl/wave.do
project_1/project_1.ip_user_files/sim_scripts/schematic/ies/
project_1/project_1.ip_user_files/sim_scripts/schematic/ies/file_info.txt
project_1/project_1.ip_user_files/sim_scripts/schematic/ies/README.txt
project_1/project_1.ip_user_files/sim_scripts/schematic/ies/run.f
project_1/project_1.ip_user_files/sim_scripts/schematic/ies/schematic.sh
project_1/project_1.ip_user_files/sim_scripts/schematic/modelsim/
project_1/project_1.ip_user_files/sim_scripts/schematic/modelsim/compile.do
project_1/project_1.ip_user_files/sim_scripts/schematic/modelsim/file_info.txt
project_1/project_1.ip_user_files/sim_scripts/schematic/modelsim/README.txt
project_1/project_1.ip_user_files/sim_scripts/schematic/modelsim/schematic.sh
project_1/project_1.ip_user_files/sim_scripts/schematic/modelsim/schematic.udo
project_1/project_1.ip_user_files/sim_scripts/schematic/modelsim/simulate.do
project_1/project_1.ip_user_files/sim_scripts/schematic/modelsim/wave.do
project_1/project_1.ip_user_files/sim_scripts/schematic/questa/
project_1/project_1.ip_user_files/sim_scripts/schematic/questa/compile.do
project_1/project_1.ip_user_files/sim_scripts/schematic/questa/elaborate.do
project_1/project_1.ip_user_files/sim_scripts/schematic/questa/file_info.txt
project_1/project_1.ip_user_files/sim_scripts/schematic/questa/README.txt
project_1/project_1.ip_user_files/sim_scripts/schematic/questa/schematic.sh
project_1/project_1.ip_user_files/sim_scripts/schematic/questa/schematic.udo
project_1/project_1.ip_user_files/sim_scripts/schematic/questa/simulate.do
project_1/project_1.ip_user_files/sim_scripts/schematic/questa/wave.do
project_1/project_1.ip_user_files/sim_scripts/schematic/README.txt
project_1/project_1.ip_user_files/sim_scripts/schematic/riviera/
project_1/project_1.ip_user_files/sim_scripts/schematic/riviera/compile.do
project_1/project_1.ip_user_files/sim_scripts/schematic/riviera/file_info.txt
project_1/project_1.ip_user_files/sim_scripts/schematic/riviera/README.txt
project_1/project_1.ip_user_files/sim_scripts/schematic/riviera/schematic.sh
project_1/project_1.ip_user_files/sim_scripts/schematic/riviera/schematic.udo
project_1/project_1.ip_user_files/sim_scripts/schematic/riviera/simulate.do
project_1/project_1.ip_user_files/sim_scripts/schematic/riviera/wave.do
project_1/project_1.ip_user_files/sim_scripts/schematic/vcs/
project_1/project_1.ip_user_files/sim_scripts/schematic/vcs/file_info.txt
project_1/project_1.ip_user_files/sim_scripts/schematic/vcs/README.txt
project_1/project_1.ip_user_files/sim_scripts/schematic/vcs/schematic.sh
project_1/project_1.ip_user_files/sim_scripts/schematic/vcs/simulate.do
project_1/project_1.ip_user_files/sim_scripts/schematic/xsim/
project_1/project_1.ip_user_files/sim_scripts/schematic/xsim/cmd.tcl
project_1/projec

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