文件名称:VGA
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所属分类:
- 标签属性:
- 上传时间:2017-03-31
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文件大小:21.53mb
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已下载:0次
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提 供 者:
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相关连接:无下载说明:别用迅雷下载,失败请重下,重下不扣分!
介绍说明--下载内容来自于网络,使用问题请自行百度
VGA显示彩条,作为调试VGA接口的小程序。完整工程奉上。-VGA display color bars as small debugging VGA connector. Complete engineering offer.
(系统自动生成,下载前可以参看下载内容)
下载文件列表
VGA/
VGA/c5_pin_model_dump.txt
VGA/cio_dump_disallowed_lists.echo
VGA/clk20M.vhd
VGA/clk20M.vhd.bak
VGA/db/
VGA/db/logic_util_heursitic.dat
VGA/db/prev_cmp_VGA.qmsg
VGA/db/VGA.(0).cnf.cdb
VGA/db/VGA.(0).cnf.hdb
VGA/db/VGA.(1).cnf.cdb
VGA/db/VGA.(1).cnf.hdb
VGA/db/VGA.(2).cnf.cdb
VGA/db/VGA.(2).cnf.hdb
VGA/db/VGA.asm.qmsg
VGA/db/VGA.asm.rdb
VGA/db/VGA.cbx.xml
VGA/db/VGA.cmp.bpm
VGA/db/VGA.cmp.cdb
VGA/db/VGA.cmp.hdb
VGA/db/VGA.cmp.idb
VGA/db/VGA.cmp.kpt
VGA/db/VGA.cmp.logdb
VGA/db/VGA.cmp.rdb
VGA/db/VGA.cmp_merge.kpt
VGA/db/VGA.cyclonev_io_sim_cache.ff_0c_fast.hsd
VGA/db/VGA.cyclonev_io_sim_cache.ff_85c_fast.hsd
VGA/db/VGA.cyclonev_io_sim_cache.ss_0c_slow.hsd
VGA/db/VGA.cyclonev_io_sim_cache.ss_85c_slow.hsd
VGA/db/VGA.db_info
VGA/db/VGA.eda.qmsg
VGA/db/VGA.fit.qmsg
VGA/db/VGA.hier_info
VGA/db/VGA.hif
VGA/db/VGA.ipinfo
VGA/db/VGA.lpc.html
VGA/db/VGA.lpc.rdb
VGA/db/VGA.lpc.txt
VGA/db/VGA.map.ammdb
VGA/db/VGA.map.bpm
VGA/db/VGA.map.cdb
VGA/db/VGA.map.hdb
VGA/db/VGA.map.kpt
VGA/db/VGA.map.logdb
VGA/db/VGA.map.qmsg
VGA/db/VGA.map.rdb
VGA/db/VGA.map_bb.cdb
VGA/db/VGA.map_bb.hdb
VGA/db/VGA.map_bb.logdb
VGA/db/VGA.pplq.rdb
VGA/db/VGA.pre_map.hdb
VGA/db/VGA.pti_db_list.ddb
VGA/db/VGA.root_partition.map.reg_db.cdb
VGA/db/VGA.routing.rdb
VGA/db/VGA.rpp.qmsg
VGA/db/VGA.rtlv.hdb
VGA/db/VGA.rtlv_sg.cdb
VGA/db/VGA.rtlv_sg_swap.cdb
VGA/db/VGA.sgate.rvd
VGA/db/VGA.sgate_sm.rvd
VGA/db/VGA.sld_design_entry.sci
VGA/db/VGA.sld_design_entry_dsc.sci
VGA/db/VGA.smart_action.txt
VGA/db/VGA.sta.qmsg
VGA/db/VGA.sta.rdb
VGA/db/VGA.sta_cmp.8_slow_1100mv_85c.tdb
VGA/db/VGA.syn_hier_info
VGA/db/VGA.tiscmp.fastest_slow_1100mv_0c.ddb
VGA/db/VGA.tiscmp.fastest_slow_1100mv_85c.ddb
VGA/db/VGA.tiscmp.fast_1100mv_0c.ddb
VGA/db/VGA.tiscmp.fast_1100mv_85c.ddb
VGA/db/VGA.tiscmp.slow_1100mv_0c.ddb
VGA/db/VGA.tiscmp.slow_1100mv_85c.ddb
VGA/db/VGA.tis_db_list.ddb
VGA/db/VGA.tmw_info
VGA/db/VGA.vpr.ammdb
VGA/hc_output/
VGA/hc_output/VGA.names_drv_tbl
VGA/incremental_db/
VGA/incremental_db/compiled_partitions/
VGA/incremental_db/compiled_partitions/VGA.db_info
VGA/incremental_db/compiled_partitions/VGA.root_partition.cmp.ammdb
VGA/incremental_db/compiled_partitions/VGA.root_partition.cmp.cdb
VGA/incremental_db/compiled_partitions/VGA.root_partition.cmp.dfp
VGA/incremental_db/compiled_partitions/VGA.root_partition.cmp.hbdb.cdb
VGA/incremental_db/compiled_partitions/VGA.root_partition.cmp.hbdb.hdb
VGA/incremental_db/compiled_partitions/VGA.root_partition.cmp.hbdb.sig
VGA/incremental_db/compiled_partitions/VGA.root_partition.cmp.hdb
VGA/incremental_db/compiled_partitions/VGA.root_partition.cmp.kpt
VGA/incremental_db/compiled_partitions/VGA.root_partition.cmp.logdb
VGA/incremental_db/compiled_partitions/VGA.root_partition.cmp.rcfdb
VGA/incremental_db/compiled_partitions/VGA.root_partition.map.cdb
VGA/incremental_db/compiled_partitions/VGA.root_partition.map.dpi
VGA/incremental_db/compiled_partitions/VGA.root_partition.map.hbdb.cdb
VGA/incremental_db/compiled_partitions/VGA.root_partition.map.hbdb.hb_info
VGA/incremental_db/compiled_partitions/VGA.root_partition.map.hbdb.hdb
VGA/incremental_db/compiled_partitions/VGA.root_partition.map.hbdb.sig
VGA/incremental_db/compiled_partitions/VGA.root_partition.map.hdb
VGA/incremental_db/compiled_partitions/VGA.root_partition.map.kpt
VGA/incremental_db/README
VGA/output_files/
VGA/output_files/VGA.asm.rpt
VGA/output_files/VGA.cdf
VGA/output_files/VGA.done
VGA/output_files/VGA.eda.rpt
VGA/output_files/VGA.fit.rpt
VGA/output_files/VGA.fit.smsg
VGA/output_files/VGA.fit.summary
VGA/output_files/VGA.flow.rpt
VGA/output_files/VGA.jdi
VGA/output_files/VGA.map.rpt
VGA/output_files/VGA.map.summary
VGA/output_files/VGA.pin
VGA/output_files/VGA.sof
VGA/output_files/VGA.sta.rpt
VGA/output_files/VGA.sta.summary
VGA/simulation/
VGA/simulation/modelsim/
VGA/simulation/modelsim/modelsim.ini
VGA/simulation/modelsim/msim_transcript
VGA/simulation/modelsim/rtl_work/
VGA/simulation/modelsim/rtl_work/@_opt/
VGA/simulation/modelsim/rtl_work/@_opt/_lib.qdb
VGA/simulation/modelsim/rtl_work/@_opt/_lib1_0.qdb
VGA/simulation/modelsim/rtl_work/@_opt/_lib1_0.qpg
VGA/simulation/modelsim/rtl_work/@_opt/_lib2_0.qdb
VGA/simulation/modelsim/rtl_work/@_opt/_lib2_0.qpg
VGA/simulation/modelsim/rtl_work/@_opt/_lib3_0.qdb
VGA/simulation/modelsim/rtl_work/@_opt/_lib3_0.qpg
VGA/simulation/modelsim/rtl_work/@_opt/_lib4_0.qdb
VGA/simulation/modelsim/rtl_work/@_opt/_lib4_0.qpg
VGA/simulation/modelsim/rtl_work/_info
VGA/simulation/modelsim/rtl_work/_lib.qdb
VGA/simulation/modelsim/rtl_work/_lib1_0.qdb
VGA/simulation/modelsim/rtl_work/_lib1_0.qpg
VGA/simulation/modelsim/rtl_work/_vmake
VGA/simulation/modelsim/VGA_run_msim_rtl_vhdl.do
VGA/simulation/modelsim/VGA_run_msim_rtl_vhdl.do.bak
VGA/simulation/modelsim/VGA_run_msim_rtl_vhdl.do.bak1
VGA/simulation/modelsim/VGA_run_msim_rtl_vhdl.do.bak10
VGA/simulation/modelsim/VGA_run_msim_rtl_vhdl.do.bak11
VGA/simulation/modelsim/VGA_run_msim_rtl_vhdl.do.bak2
VGA/simulation/modelsim/VGA_run_msim_rtl_vhdl.do.bak3
VGA/simulation/modelsim/VGA_run_msim_rtl_vhdl.do.bak4
VGA/simulation/modelsim/VGA_run_msim_rtl_vhdl.do.bak5
VGA/simulation/modelsim
VGA/c5_pin_model_dump.txt
VGA/cio_dump_disallowed_lists.echo
VGA/clk20M.vhd
VGA/clk20M.vhd.bak
VGA/db/
VGA/db/logic_util_heursitic.dat
VGA/db/prev_cmp_VGA.qmsg
VGA/db/VGA.(0).cnf.cdb
VGA/db/VGA.(0).cnf.hdb
VGA/db/VGA.(1).cnf.cdb
VGA/db/VGA.(1).cnf.hdb
VGA/db/VGA.(2).cnf.cdb
VGA/db/VGA.(2).cnf.hdb
VGA/db/VGA.asm.qmsg
VGA/db/VGA.asm.rdb
VGA/db/VGA.cbx.xml
VGA/db/VGA.cmp.bpm
VGA/db/VGA.cmp.cdb
VGA/db/VGA.cmp.hdb
VGA/db/VGA.cmp.idb
VGA/db/VGA.cmp.kpt
VGA/db/VGA.cmp.logdb
VGA/db/VGA.cmp.rdb
VGA/db/VGA.cmp_merge.kpt
VGA/db/VGA.cyclonev_io_sim_cache.ff_0c_fast.hsd
VGA/db/VGA.cyclonev_io_sim_cache.ff_85c_fast.hsd
VGA/db/VGA.cyclonev_io_sim_cache.ss_0c_slow.hsd
VGA/db/VGA.cyclonev_io_sim_cache.ss_85c_slow.hsd
VGA/db/VGA.db_info
VGA/db/VGA.eda.qmsg
VGA/db/VGA.fit.qmsg
VGA/db/VGA.hier_info
VGA/db/VGA.hif
VGA/db/VGA.ipinfo
VGA/db/VGA.lpc.html
VGA/db/VGA.lpc.rdb
VGA/db/VGA.lpc.txt
VGA/db/VGA.map.ammdb
VGA/db/VGA.map.bpm
VGA/db/VGA.map.cdb
VGA/db/VGA.map.hdb
VGA/db/VGA.map.kpt
VGA/db/VGA.map.logdb
VGA/db/VGA.map.qmsg
VGA/db/VGA.map.rdb
VGA/db/VGA.map_bb.cdb
VGA/db/VGA.map_bb.hdb
VGA/db/VGA.map_bb.logdb
VGA/db/VGA.pplq.rdb
VGA/db/VGA.pre_map.hdb
VGA/db/VGA.pti_db_list.ddb
VGA/db/VGA.root_partition.map.reg_db.cdb
VGA/db/VGA.routing.rdb
VGA/db/VGA.rpp.qmsg
VGA/db/VGA.rtlv.hdb
VGA/db/VGA.rtlv_sg.cdb
VGA/db/VGA.rtlv_sg_swap.cdb
VGA/db/VGA.sgate.rvd
VGA/db/VGA.sgate_sm.rvd
VGA/db/VGA.sld_design_entry.sci
VGA/db/VGA.sld_design_entry_dsc.sci
VGA/db/VGA.smart_action.txt
VGA/db/VGA.sta.qmsg
VGA/db/VGA.sta.rdb
VGA/db/VGA.sta_cmp.8_slow_1100mv_85c.tdb
VGA/db/VGA.syn_hier_info
VGA/db/VGA.tiscmp.fastest_slow_1100mv_0c.ddb
VGA/db/VGA.tiscmp.fastest_slow_1100mv_85c.ddb
VGA/db/VGA.tiscmp.fast_1100mv_0c.ddb
VGA/db/VGA.tiscmp.fast_1100mv_85c.ddb
VGA/db/VGA.tiscmp.slow_1100mv_0c.ddb
VGA/db/VGA.tiscmp.slow_1100mv_85c.ddb
VGA/db/VGA.tis_db_list.ddb
VGA/db/VGA.tmw_info
VGA/db/VGA.vpr.ammdb
VGA/hc_output/
VGA/hc_output/VGA.names_drv_tbl
VGA/incremental_db/
VGA/incremental_db/compiled_partitions/
VGA/incremental_db/compiled_partitions/VGA.db_info
VGA/incremental_db/compiled_partitions/VGA.root_partition.cmp.ammdb
VGA/incremental_db/compiled_partitions/VGA.root_partition.cmp.cdb
VGA/incremental_db/compiled_partitions/VGA.root_partition.cmp.dfp
VGA/incremental_db/compiled_partitions/VGA.root_partition.cmp.hbdb.cdb
VGA/incremental_db/compiled_partitions/VGA.root_partition.cmp.hbdb.hdb
VGA/incremental_db/compiled_partitions/VGA.root_partition.cmp.hbdb.sig
VGA/incremental_db/compiled_partitions/VGA.root_partition.cmp.hdb
VGA/incremental_db/compiled_partitions/VGA.root_partition.cmp.kpt
VGA/incremental_db/compiled_partitions/VGA.root_partition.cmp.logdb
VGA/incremental_db/compiled_partitions/VGA.root_partition.cmp.rcfdb
VGA/incremental_db/compiled_partitions/VGA.root_partition.map.cdb
VGA/incremental_db/compiled_partitions/VGA.root_partition.map.dpi
VGA/incremental_db/compiled_partitions/VGA.root_partition.map.hbdb.cdb
VGA/incremental_db/compiled_partitions/VGA.root_partition.map.hbdb.hb_info
VGA/incremental_db/compiled_partitions/VGA.root_partition.map.hbdb.hdb
VGA/incremental_db/compiled_partitions/VGA.root_partition.map.hbdb.sig
VGA/incremental_db/compiled_partitions/VGA.root_partition.map.hdb
VGA/incremental_db/compiled_partitions/VGA.root_partition.map.kpt
VGA/incremental_db/README
VGA/output_files/
VGA/output_files/VGA.asm.rpt
VGA/output_files/VGA.cdf
VGA/output_files/VGA.done
VGA/output_files/VGA.eda.rpt
VGA/output_files/VGA.fit.rpt
VGA/output_files/VGA.fit.smsg
VGA/output_files/VGA.fit.summary
VGA/output_files/VGA.flow.rpt
VGA/output_files/VGA.jdi
VGA/output_files/VGA.map.rpt
VGA/output_files/VGA.map.summary
VGA/output_files/VGA.pin
VGA/output_files/VGA.sof
VGA/output_files/VGA.sta.rpt
VGA/output_files/VGA.sta.summary
VGA/simulation/
VGA/simulation/modelsim/
VGA/simulation/modelsim/modelsim.ini
VGA/simulation/modelsim/msim_transcript
VGA/simulation/modelsim/rtl_work/
VGA/simulation/modelsim/rtl_work/@_opt/
VGA/simulation/modelsim/rtl_work/@_opt/_lib.qdb
VGA/simulation/modelsim/rtl_work/@_opt/_lib1_0.qdb
VGA/simulation/modelsim/rtl_work/@_opt/_lib1_0.qpg
VGA/simulation/modelsim/rtl_work/@_opt/_lib2_0.qdb
VGA/simulation/modelsim/rtl_work/@_opt/_lib2_0.qpg
VGA/simulation/modelsim/rtl_work/@_opt/_lib3_0.qdb
VGA/simulation/modelsim/rtl_work/@_opt/_lib3_0.qpg
VGA/simulation/modelsim/rtl_work/@_opt/_lib4_0.qdb
VGA/simulation/modelsim/rtl_work/@_opt/_lib4_0.qpg
VGA/simulation/modelsim/rtl_work/_info
VGA/simulation/modelsim/rtl_work/_lib.qdb
VGA/simulation/modelsim/rtl_work/_lib1_0.qdb
VGA/simulation/modelsim/rtl_work/_lib1_0.qpg
VGA/simulation/modelsim/rtl_work/_vmake
VGA/simulation/modelsim/VGA_run_msim_rtl_vhdl.do
VGA/simulation/modelsim/VGA_run_msim_rtl_vhdl.do.bak
VGA/simulation/modelsim/VGA_run_msim_rtl_vhdl.do.bak1
VGA/simulation/modelsim/VGA_run_msim_rtl_vhdl.do.bak10
VGA/simulation/modelsim/VGA_run_msim_rtl_vhdl.do.bak11
VGA/simulation/modelsim/VGA_run_msim_rtl_vhdl.do.bak2
VGA/simulation/modelsim/VGA_run_msim_rtl_vhdl.do.bak3
VGA/simulation/modelsim/VGA_run_msim_rtl_vhdl.do.bak4
VGA/simulation/modelsim/VGA_run_msim_rtl_vhdl.do.bak5
VGA/simulation/modelsim
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