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文件名称:aes_core

  • 所属分类：
    加密解密
  • 标签属性：
    [PDF]
  • 上传时间：
    2008-10-13
  • 文件大小：
    77.77kb
  • 已下载：
    0次
  • 提 供 者：
    yuans*****
  • 相关连接：
    无
  • 下载说明：
    别用迅雷下载，失败请重下，重下不扣分！
修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

Verilog实现AES加密算法

密码模块作为安全保密系统的重要组成部分，其核心任务就是加密数据。分组密码算法AES以其高效率、低开销、实现简单等特点目前被广泛应用于密码模块的研制中。密码模块一般被设计成外接在主机串口或并口的一个硬件设备或是一块插卡，具有速度快，低时延的特点。而从整体发展趋势来看，嵌入式密码模块由于灵活，适用于多种用户终端、通信设备和武器平台，将会得到更加广泛的应用
(系统自动生成,下载前可以参看下载内容)

下载文件列表

aes_core/bench/CVS/Entries
aes_core/bench/CVS/Repository
aes_core/bench/CVS/Root
aes_core/bench/verilog/CVS/Entries
aes_core/bench/verilog/CVS/Repository
aes_core/bench/verilog/CVS/Root
aes_core/bench/verilog/test_bench_top.v
aes_core/CVS/Entries
aes_core/CVS/Repository
aes_core/CVS/Root
aes_core/doc/aes.pdf
aes_core/doc/CVS/Entries
aes_core/doc/CVS/Repository
aes_core/doc/CVS/Root
aes_core/rtl/CVS/Entries
aes_core/rtl/CVS/Repository
aes_core/rtl/CVS/Root
aes_core/rtl/verilog/aes_cipher_top.v
aes_core/rtl/verilog/aes_inv_cipher_top.v
aes_core/rtl/verilog/aes_inv_sbox.v
aes_core/rtl/verilog/aes_key_expand_128.v
aes_core/rtl/verilog/aes_rcon.v
aes_core/rtl/verilog/aes_sbox.v
aes_core/rtl/verilog/CVS/Entries
aes_core/rtl/verilog/CVS/Repository
aes_core/rtl/verilog/CVS/Root
aes_core/rtl/verilog/timescale.v
aes_core/sim/CVS/Entries
aes_core/sim/CVS/Repository
aes_core/sim/CVS/Root
aes_core/sim/rtl_sim/bin/CVS/Entries
aes_core/sim/rtl_sim/bin/CVS/Repository
aes_core/sim/rtl_sim/bin/CVS/Root
aes_core/sim/rtl_sim/bin/Makefile
aes_core/sim/rtl_sim/CVS/Entries
aes_core/sim/rtl_sim/CVS/Repository
aes_core/sim/rtl_sim/CVS/Root
aes_core/sim/rtl_sim/run/CVS/Entries
aes_core/sim/rtl_sim/run/CVS/Repository
aes_core/sim/rtl_sim/run/CVS/Root
aes_core/sim/rtl_sim/run/waves/CVS/Entries
aes_core/sim/rtl_sim/run/waves/CVS/Repository
aes_core/sim/rtl_sim/run/waves/CVS/Root
aes_core/sim/rtl_sim/run/waves/waves.do
aes_core/syn/bin/comp.dc
aes_core/syn/bin/CVS/Entries
aes_core/syn/bin/CVS/Repository
aes_core/syn/bin/CVS/Root
aes_core/syn/bin/design_spec.dc
aes_core/syn/bin/lib_spec.dc
aes_core/syn/bin/read.dc
aes_core/syn/CVS/Entries
aes_core/syn/CVS/Repository
aes_core/syn/CVS/Root
aes_core/vim_session.vim
aes_core/sim/rtl_sim/run/waves/CVS
aes_core/sim/rtl_sim/bin/CVS
aes_core/sim/rtl_sim/run/CVS
aes_core/sim/rtl_sim/run/waves
aes_core/bench/verilog/CVS
aes_core/rtl/verilog/CVS
aes_core/sim/rtl_sim/bin
aes_core/sim/rtl_sim/CVS
aes_core/sim/rtl_sim/run
aes_core/syn/bin/CVS
aes_core/bench/CVS
aes_core/bench/verilog
aes_core/doc/CVS
aes_core/rtl/CVS
aes_core/rtl/verilog
aes_core/sim/CVS
aes_core/sim/rtl_sim
aes_core/syn/bin
aes_core/syn/CVS
aes_core/bench
aes_core/CVS
aes_core/doc
aes_core/rtl
aes_core/sim
aes_core/syn
aes_core

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