文件名称:三速以太网代码（FPGA）
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本代码是运用xilinx的fpga实现千兆网的，同时支持百兆以太网和10兆以太网。内含仿真文件
相关搜索： FPGA xilinx
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压缩包 : ethernet_.tar.gz 列表 ethernet_tri_mode/ ethernet_tri_mode/tags/ ethernet_tri_mode/tags/release-1-0/ ethernet_tri_mode/tags/release-1-0/start.tcl ethernet_tri_mode/tags/release-1-0/doc/ ethernet_tri_mode/tags/release-1-0/doc/Tri-mode_Ethernet_MAC_Verification_plan.pdf ethernet_tri_mode/tags/release-1-0/doc/Tri-mode_Ethernet_MAC_Specifications.pdf ethernet_tri_mode/tags/release-1-0/sim/ ethernet_tri_mode/tags/release-1-0/sim/rtl_sim/ ethernet_tri_mode/tags/release-1-0/sim/rtl_sim/ncsim_sim/ ethernet_tri_mode/tags/release-1-0/sim/rtl_sim/ncsim_sim/script/ ethernet_tri_mode/tags/release-1-0/sim/rtl_sim/ncsim_sim/script/filesel.tcl ethernet_tri_mode/tags/release-1-0/sim/rtl_sim/ncsim_sim/script/start_verify.tcl ethernet_tri_mode/tags/release-1-0/sim/rtl_sim/ncsim_sim/script/run_proc.tcl ethernet_tri_mode/tags/release-1-0/sim/rtl_sim/ncsim_sim/script/set_reg_data.tcl ethernet_tri_mode/tags/release-1-0/sim/rtl_sim/ncsim_sim/script/user_lib.tcl ethernet_tri_mode/tags/release-1-0/sim/rtl_sim/ncsim_sim/script/batch_mode.tcl ethernet_tri_mode/tags/release-1-0/sim/rtl_sim/ncsim_sim/script/run.tcl ethernet_tri_mode/tags/release-1-0/sim/rtl_sim/ncsim_sim/script/set_stimulus.tcl ethernet_tri_mode/tags/release-1-0/sim/rtl_sim/ncsim_sim/bin/ ethernet_tri_mode/tags/release-1-0/sim/rtl_sim/ncsim_sim/bin/config.ini ethernet_tri_mode/tags/release-1-0/sim/rtl_sim/ncsim_sim/bin/ip_32W_check.dll ethernet_tri_mode/tags/release-1-0/sim/rtl_sim/ncsim_sim/bin/hdl.var ethernet_tri_mode/tags/release-1-0/sim/rtl_sim/ncsim_sim/bin/vlog.list ethernet_tri_mode/tags/release-1-0/sim/rtl_sim/ncsim_sim/bin/ip_32W_check_vpi.dll ethernet_tri_mode/tags/release-1-0/sim/rtl_sim/ncsim_sim/bin/ip_32W_gen.dll ethernet_tri_mode/tags/release-1-0/sim/rtl_sim/ncsim_sim/bin/sim.nc ethernet_tri_mode/tags/release-1-0/sim/rtl_sim/ncsim_sim/bin/cds.lib ethernet_tri_mode/tags/release-1-0/sim/rtl_sim/ncsim_sim/bin/ip_32W_gen_vpi.dll ethernet_tri_mode/tags/release-1-0/sim/rtl_sim/ncsim_sim/bin/com.nc ethernet_tri_mode/tags/release-1-0/sim/rtl_sim/ncsim_sim/bin/sim_only.nc ethernet_tri_mode/tags/release-1-0/sim/rtl_sim/ncsim_sim/log/ ethernet_tri_mode/tags/release-1-0/sim/rtl_sim/ncsim_sim/log/ncsim.log ethernet_tri_mode/tags/release-1-0/sim/rtl_sim/ncsim_sim/data/ ethernet_tri_mode/tags/release-1-0/sim/rtl_sim/ncsim_sim/data/config.ini ethernet_tri_mode/tags/release-1-0/sim/rtl_sim/ncsim_sim/data/10Mbps_duplex.vec ethernet_tri_mode/tags/release-1-0/sim/rtl_sim/ncsim_sim/data/source_mac_replace.vec ethernet_tri_mode/tags/release-1-0/sim/rtl_sim/ncsim_sim/data/CPU.vec ethernet_tri_mode/tags/release-1-0/sim/rtl_sim/ncsim_sim/data/100Mbps_duplex.vec ethernet_tri_mode/tags/release-1-0/sim/rtl_sim/ncsim_sim/data/target_mac_check.vec ethernet_tri_mode/tags/release-1-0/sim/rtl_sim/ncsim_sim/data/batch.dat ethernet_tri_mode/tags/release-1-0/sim/rtl_sim/ncsim_sim/data/flow_ctrl.vec ethernet_tri_mode/tags/release-1-0/sim/rtl_sim/ncsim_sim/data/46-50.ini ethernet_tri_mode/tags/release-1-0/sim/rtl_sim/ncsim_sim/data/1000Mbps_duplex.vec ethernet_tri_mode/tags/release-1-0/bench/ ethernet_tri_mode/tags/release-1-0/bench/verilog/ ethernet_tri_mode/tags/release-1-0/bench/verilog/host_sim.v ethernet_tri_mode/tags/release-1-0/bench/verilog/User_int_sim.v ethernet_tri_mode/tags/release-1-0/bench/verilog/Phy_sim.v ethernet_tri_mode/tags/release-1-0/bench/verilog/reg_int_sim.v ethernet_tri_mode/tags/release-1-0/bench/verilog/altera_mf.v ethernet_tri_mode/tags/release-1-0/bench/verilog/tb_top.v ethernet_tri_mode/tags/release-1-0/syn/ ethernet_tri_mode/tags/release-1-0/syn/syn.prj ethernet_tri_mode/tags/release-1-0/rtl/ ethernet_tri_mode/tags/release-1-0/rtl/verilog/ ethernet_tri_mode/tags/release-1-0/rtl/verilog/MAC_tx/ ethernet_tri_mode/tags/release-1-0/rtl/verilog/MAC_tx/MAC_tx_addr_add.v ethernet_tri_mode/tags/release-1-0/rtl/verilog/MAC_tx/flow_ctrl.v ethernet_tri_mode/tags/release-1-0/rtl/verilog/MAC_tx/MAC_tx_FF.v ethernet_tri_mode/tags/release-1-0/rtl/verilog/MAC_tx/MAC_tx_Ctrl.v ethernet_tri_mode/tags/release-1-0/rtl/verilog/MAC_tx/Ramdon_gen.v ethernet_tri_mode/tags/release-1-0/rtl/verilog/MAC_tx/CRC_gen.v ethernet_tri_mode/tags/release-1-0/rtl/verilog/Phy_int.v ethernet_tri_mode/tags/release-1-0/rtl/verilog/MAC_rx.v ethernet_tri_mode/tags/release-1-0/rtl/verilog/miim/ ethernet_tri_mode/tags/release-1-0/rtl/verilog/miim/timescale.v ethernet_tri_mode/tags/release-1-0/rtl/verilog/miim/eth_clockgen.v ethernet_tri_mode/tags/release-1-0/rtl/verilog/miim/eth_outputcontrol.v ethernet_tri_mode/tags/release-1-0/rtl/verilog/miim/eth_shiftreg.v ethernet_tri_mode/tags/release-1-0/rtl/verilog/RMON.v ethernet_tri_mode/tags/release-1-0/rtl/verilog/Clk_ctrl.v ethernet_tri_mode/tags/release-1-0/rtl/verilog/MAC_tx.v ethernet_tri_mode/tags/release-1-0/rtl/verilog/TECH/ ethernet_tri_mode/tags/release-1-0/rtl/verilog/TECH/CLK_SWITCH.v ethernet_tri_mode/tags/release-1-0/rtl/verilog/TECH/CLK_DIV2.v ethernet_tri_mode/tags/release-1-0/rtl/verilog/TECH/duram.v ethernet_tri_mode/tags/release-1-0/rtl/verilog/TECH/afifo.v ethernet_tri_mode/tags/release-1-0/rtl/verilog/reg_int.v ethernet_tri_mode/tags/release-1-0/rtl/verilog/RMON/ ethernet_tri_mo
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