文件名称:FPGA_phase_lock_demodulation
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- 上传时间:2017-04-12
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文件大小:45.32mb
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已下载:2次
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FPGA 用Verilog语言实现数字锁相解调系统,包含了正交的DDS函数发生器和相应的AD驱动-FPGA digital demodulation system in Verilog lock, comprising a DDS orthogonal function generator and driving the corresponding AD
(系统自动生成,下载前可以参看下载内容)
下载文件列表
last1
.....\.metadata
.....\.........\.lock
.....\.........\.log
.....\.........\.mylyn
.....\.........\......\contexts
.....\.........\......\repositories.xml.zip
.....\.........\.plugins
.....\.........\........\org.eclipse.cdt.core
.....\.........\........\....................\.log
.....\.........\........\....................\VGA.1396680935831.pdom
.....\.........\........\....................\VGA_bsp.1396680929611.pdom
.....\.........\........\org.eclipse.cdt.make.core
.....\.........\........\.........................\.log
.....\.........\........\.........................\specs.c
.....\.........\........\.........................\specs.cpp
.....\.........\........\.........................\VGA.sc
.....\.........\........\.........................\VGA_bsp.sc
.....\.........\........\org.eclipse.cdt.managedbuilder.core
.....\.........\........\org.eclipse.cdt.ui
.....\.........\........\..................\dialog_settings.xml
.....\.........\........\..................\global-build.log
.....\.........\........\..................\VGA.build.log
.....\.........\........\..................\VGA_bsp.build.log
.....\.........\........\org.eclipse.core.resources
.....\.........\........\..........................\.history
.....\.........\........\..........................\........\2a
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.....\.........\........\..........................\........\39
.....\.........\........\..........................\........\..\2085453296bc00131f26b755012cfae2
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.....\.........\........\..........................\........\6d
.....\.........\........\..........................\........\..\a0e7fb5499bc00131f26b755012cfae2
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.....\.........\........\..........................\........\..\20acb1be99bc00131f26b755012cfae2
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.....\.........\........\..........................\........\..\b08640f398bc00131f26b755012cfae2
.....\.........\........\..........................\.projects
.....\.........\........\..........................\.........\VGA
.....\.........\........\..........................\.........\...\.indexes
.....\.........\........\..........................\.........\...\........\c9
.....\.........\........\..........................\.........\...\........\..\history.index
.....\.........\........\..........................\.........\...\........\..\properties.index
.....\.........\........\..........................\.........\...\........\properties.index
.....\.........\........\..........................\.........\...\.location
.....\.........\........\..........................\.........\VGA_bsp
.....\.........\........\..........................\.........\.......\.indexes
.....\.........\........\..........................\.........\.......\........\properties.index
.....\.........\........\..........................\.........\.......\.location
.....\.........\........\..........................\.root
.....\.........\........\..........................\.....\.indexes
.....\.........\........\..........................\.....\........\history.version
.....\.........\........\..........................\.....\........\properties.index
.....\.........\........\..........................\.....\........\properties.version
.....\.........\........\..........................\.....\1.tree
.....\.........\........\..........................\.safetable
.....\.........\........\..........................\..........\org.eclipse.core.resources
.....\.........\........\org.eclipse.core.runtime
.....\.........\........\........................\.settings
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