用 Farrow 结构滤波器对并行采样信号进行时间误差校正, 通过 DSPBuilder 软件将设计的滤波器模型转化为硬

件语言, 利于 FPGA 实现-The Farrow filter is used to correct the time error of the parallel sampling signal, and the designed filter model is converted to hard by DSPBuilder software







Language, conducive to the realization of FPGA