文件名称:ds1302
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- 上传时间：2017-04-24
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文件大小：3.61mb
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利用DS1302芯片实现RTC（Real Time Clock，实时时钟）功能。驱动DS1302芯片，给芯片赋初始值，并通过LED灯显示DS1302的实时个位秒数（0~9）。-Realize RTC (Real Time Clock) function with DS1302 chip. Drive DS1302 chip, give the chip initial value, and through the LED display DS1302 real-time seconds (0 ~ 9).
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下载文件列表
18_ds1302
.........\18_ds1302
.........\.........\db
.........\.........\..\add_sub_7pc.tdf
.........\.........\..\add_sub_8pc.tdf
.........\.........\..\alt_u_div_a4f.tdf
.........\.........\..\logic_util_heursitic.dat
.........\.........\..\lpm_divide_jhm.tdf
.........\.........\..\lpm_divide_m9m.tdf
.........\.........\..\pll_module_altpll.v
.........\.........\..\prev_cmp_Verilog_Prj.qmsg
.........\.........\..\sign_div_unsign_bkh.tdf
.........\.........\..\Verilog_Prj.amm.cdb
.........\.........\..\Verilog_Prj.asm.qmsg
.........\.........\..\Verilog_Prj.asm.rdb
.........\.........\..\Verilog_Prj.asm_labs.ddb
.........\.........\..\Verilog_Prj.cbx.xml
.........\.........\..\Verilog_Prj.cmp.bpm
.........\.........\..\Verilog_Prj.cmp.cdb
.........\.........\..\Verilog_Prj.cmp.hdb
.........\.........\..\Verilog_Prj.cmp.kpt
.........\.........\..\Verilog_Prj.cmp.logdb
.........\.........\..\Verilog_Prj.cmp.rdb
.........\.........\..\Verilog_Prj.cmp_merge.kpt
.........\.........\..\Verilog_Prj.cycloneive_io_sim_cache.45um_ff_1200mv_0c_fast.hsd
.........\.........\..\Verilog_Prj.cycloneive_io_sim_cache.45um_ss_1200mv_0c_slow.hsd
.........\.........\..\Verilog_Prj.cycloneive_io_sim_cache.45um_ss_1200mv_85c_slow.hsd
.........\.........\..\Verilog_Prj.db_info
.........\.........\..\Verilog_Prj.fit.qmsg
.........\.........\..\Verilog_Prj.hier_info
.........\.........\..\Verilog_Prj.hif
.........\.........\..\Verilog_Prj.idb.cdb
.........\.........\..\Verilog_Prj.lpc.html
.........\.........\..\Verilog_Prj.lpc.rdb
.........\.........\..\Verilog_Prj.lpc.txt
.........\.........\..\Verilog_Prj.map.bpm
.........\.........\..\Verilog_Prj.map.cdb
.........\.........\..\Verilog_Prj.map.hdb
.........\.........\..\Verilog_Prj.map.kpt
.........\.........\..\Verilog_Prj.map.logdb
.........\.........\..\Verilog_Prj.map.qmsg
.........\.........\..\Verilog_Prj.map.rdb
.........\.........\..\Verilog_Prj.map_bb.cdb
.........\.........\..\Verilog_Prj.map_bb.hdb
.........\.........\..\Verilog_Prj.map_bb.logdb
.........\.........\..\Verilog_Prj.pre_map.cdb
.........\.........\..\Verilog_Prj.pre_map.hdb
.........\.........\..\Verilog_Prj.root_partition.map.reg_db.cdb
.........\.........\..\Verilog_Prj.routing.rdb
.........\.........\..\Verilog_Prj.rtlv.hdb
.........\.........\..\Verilog_Prj.rtlv_sg.cdb
.........\.........\..\Verilog_Prj.rtlv_sg_swap.cdb
.........\.........\..\Verilog_Prj.sgdiff.cdb
.........\.........\..\Verilog_Prj.sgdiff.hdb
.........\.........\..\Verilog_Prj.sld_design_entry.sci
.........\.........\..\Verilog_Prj.sld_design_entry_dsc.sci
.........\.........\..\Verilog_Prj.smart_action.txt
.........\.........\..\Verilog_Prj.sta.qmsg
.........\.........\..\Verilog_Prj.sta.rdb
.........\.........\..\Verilog_Prj.sta_cmp.8_slow_1200mv_85c.tdb
.........\.........\..\Verilog_Prj.syn_hier_info
.........\.........\..\Verilog_Prj.tiscmp.fastest_slow_1200mv_0c.ddb
.........\.........\..\Verilog_Prj.tiscmp.fastest_slow_1200mv_85c.ddb
.........\.........\..\Verilog_Prj.tiscmp.fast_1200mv_0c.ddb
.........\.........\..\Verilog_Prj.tiscmp.slow_1200mv_0c.ddb
.........\.........\..\Verilog_Prj.tiscmp.slow_1200mv_85c.ddb
.........\.........\..\Verilog_Prj.tis_db_list.ddb
.........\.........\..\Verilog_Prj.tmw_info
.........\.........\incremental_db
.........\.........\..............\compiled_partitions
.........\.........\..............\...................\Verilog_Prj.db_info
.........\.........\..............\...................\Verilog_Prj.root_partition.cmp.cdb
.........\.........\..............\...................\Verilog_Prj.root_partition.cmp.dfp
.........\.........\..............\...................\Verilog_Prj.root_partition.cmp.hdb
.........\.........\..............\...................\Verilog_Prj.root_partition.cmp.kpt
.........\.........\..............\...................\Verilog_Prj.root_partition.cmp.logdb
.........\.........\..............\...................\Verilog_Prj.root_partition.cmp.rcfdb
.........\.........\..............\...................\Verilog_Prj.root_partition.map.cdb
.........\.........\..............\..........
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