文件名称:code_test
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- 上传时间:2017-05-28
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文件大小:1.15mb
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已下载:1次
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uvm testbench 例子,可以在questa软件里运行,运用shell脚本,在cygwin环境中执行,非常方便-Uvm testbench example, you can run in questa software, the use of shell scr ipt, in cygwin environment, very convenient
(系统自动生成,下载前可以参看下载内容)
下载文件列表
code_test/
code_test/sim_tb/
code_test/sim_tb/sim/
code_test/sim_tb/sim/scripts/
code_test/sim_tb/sim/scripts/filelist.f
code_test/sim_tb/sim/scripts/path
code_test/sim_tb/sim/scripts/run
code_test/sim_tb/sim/scripts/tb_filelist.sv
code_test/sim_tb/sim/scripts/transcript
code_test/sim_tb/sim/scripts/view_wave
code_test/sim_tb/sim/scripts/vish_stacktrace.vstf
code_test/sim_tb/sim/sim_results/
code_test/sim_tb/sim/sim_results/my_case0/
code_test/sim_tb/sim/sim_results/my_case0/com.log
code_test/sim_tb/sim/sim_results/my_case0/modelsim.ini
code_test/sim_tb/sim/sim_results/my_case0/sim.log
code_test/sim_tb/sim/sim_results/my_case0/tb_top/
code_test/sim_tb/sim/sim_results/my_case0/tb_top/_info
code_test/sim_tb/sim/sim_results/my_case0/tb_top/_lib.qdb
code_test/sim_tb/sim/sim_results/my_case0/tb_top/_lib1_0.qdb
code_test/sim_tb/sim/sim_results/my_case0/tb_top/_lib1_0.qpg
code_test/sim_tb/sim/sim_results/my_case0/tb_top/_lib1_0.qtl
code_test/sim_tb/sim/sim_results/my_case0/tb_top/_vmake
code_test/sim_tb/sim/sim_results/my_case0/tb_top.vcd
code_test/sim_tb/tb/
code_test/sim_tb/tb/tb_code/
code_test/sim_tb/tb/tb_code/base_test.sv
code_test/sim_tb/tb/tb_code/bus_agent.sv
code_test/sim_tb/tb/tb_code/bus_driver.sv
code_test/sim_tb/tb/tb_code/bus_if.sv
code_test/sim_tb/tb/tb_code/bus_monitor.sv
code_test/sim_tb/tb/tb_code/bus_sequencer.sv
code_test/sim_tb/tb/tb_code/bus_transaction.sv
code_test/sim_tb/tb/tb_code/my_agent.sv
code_test/sim_tb/tb/tb_code/my_driver.sv
code_test/sim_tb/tb/tb_code/my_env.sv
code_test/sim_tb/tb/tb_code/my_if.sv
code_test/sim_tb/tb/tb_code/my_model.sv
code_test/sim_tb/tb/tb_code/my_monitor.sv
code_test/sim_tb/tb/tb_code/my_scoreboard.sv
code_test/sim_tb/tb/tb_code/my_sequencer.sv
code_test/sim_tb/tb/tb_code/my_transaction.sv
code_test/sim_tb/tb/tb_code/my_vsqr.sv
code_test/sim_tb/tb/tb_code/pass_or_fail.sv
code_test/sim_tb/tb/tb_code/reg_access_sequence.sv
code_test/sim_tb/tb/tb_code/tb_top.sv
code_test/sim_tb/tb/tests/
code_test/sim_tb/tb/tests/my_case0.sv
code_test/src/
code_test/src/dut.v
code_test/src/pkt_fifo_top.v
code_test/src/pkt_fir.v
code_test/src/work/
code_test/src/work/_info
code_test/src/work/_lib.qdb
code_test/src/work/_lib1_0.qdb
code_test/src/work/_lib1_0.qpg
code_test/src/work/_lib1_0.qtl
code_test/src/work/_vmake
code_test/sim_tb/
code_test/sim_tb/sim/
code_test/sim_tb/sim/scripts/
code_test/sim_tb/sim/scripts/filelist.f
code_test/sim_tb/sim/scripts/path
code_test/sim_tb/sim/scripts/run
code_test/sim_tb/sim/scripts/tb_filelist.sv
code_test/sim_tb/sim/scripts/transcript
code_test/sim_tb/sim/scripts/view_wave
code_test/sim_tb/sim/scripts/vish_stacktrace.vstf
code_test/sim_tb/sim/sim_results/
code_test/sim_tb/sim/sim_results/my_case0/
code_test/sim_tb/sim/sim_results/my_case0/com.log
code_test/sim_tb/sim/sim_results/my_case0/modelsim.ini
code_test/sim_tb/sim/sim_results/my_case0/sim.log
code_test/sim_tb/sim/sim_results/my_case0/tb_top/
code_test/sim_tb/sim/sim_results/my_case0/tb_top/_info
code_test/sim_tb/sim/sim_results/my_case0/tb_top/_lib.qdb
code_test/sim_tb/sim/sim_results/my_case0/tb_top/_lib1_0.qdb
code_test/sim_tb/sim/sim_results/my_case0/tb_top/_lib1_0.qpg
code_test/sim_tb/sim/sim_results/my_case0/tb_top/_lib1_0.qtl
code_test/sim_tb/sim/sim_results/my_case0/tb_top/_vmake
code_test/sim_tb/sim/sim_results/my_case0/tb_top.vcd
code_test/sim_tb/tb/
code_test/sim_tb/tb/tb_code/
code_test/sim_tb/tb/tb_code/base_test.sv
code_test/sim_tb/tb/tb_code/bus_agent.sv
code_test/sim_tb/tb/tb_code/bus_driver.sv
code_test/sim_tb/tb/tb_code/bus_if.sv
code_test/sim_tb/tb/tb_code/bus_monitor.sv
code_test/sim_tb/tb/tb_code/bus_sequencer.sv
code_test/sim_tb/tb/tb_code/bus_transaction.sv
code_test/sim_tb/tb/tb_code/my_agent.sv
code_test/sim_tb/tb/tb_code/my_driver.sv
code_test/sim_tb/tb/tb_code/my_env.sv
code_test/sim_tb/tb/tb_code/my_if.sv
code_test/sim_tb/tb/tb_code/my_model.sv
code_test/sim_tb/tb/tb_code/my_monitor.sv
code_test/sim_tb/tb/tb_code/my_scoreboard.sv
code_test/sim_tb/tb/tb_code/my_sequencer.sv
code_test/sim_tb/tb/tb_code/my_transaction.sv
code_test/sim_tb/tb/tb_code/my_vsqr.sv
code_test/sim_tb/tb/tb_code/pass_or_fail.sv
code_test/sim_tb/tb/tb_code/reg_access_sequence.sv
code_test/sim_tb/tb/tb_code/tb_top.sv
code_test/sim_tb/tb/tests/
code_test/sim_tb/tb/tests/my_case0.sv
code_test/src/
code_test/src/dut.v
code_test/src/pkt_fifo_top.v
code_test/src/pkt_fir.v
code_test/src/work/
code_test/src/work/_info
code_test/src/work/_lib.qdb
code_test/src/work/_lib1_0.qdb
code_test/src/work/_lib1_0.qpg
code_test/src/work/_lib1_0.qtl
code_test/src/work/_vmake
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