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pll_self_rst\sim\220model.v
pll_self_rst\sim\altera_mf.v
pll_self_rst\sim\altera_primitives.v
pll_self_rst\sim\clk_det.v
pll_self_rst\sim\modelsim.ini
pll_self_rst\sim\pll_125m.v
pll_self_rst\sim\pll_rst_ctrl.v
pll_self_rst\sim\run.bat
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pll_self_rst\sim\sgate.v
pll_self_rst\sim\tb.v
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pll_self_rst\sim\vsim.wlf
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pll_self_rst\syn\pll_rst_ctrl.prd
pll_self_rst\syn\pll_rst_ctrl.prj
pll_self_rst\syn\rev_1\AutoConstraint_pll_rst_ctrl.sdc
pll_self_rst\syn\rev_1\backup\pll_rst_ctrl.srr
pll_self_rst\syn\rev_1\dm\layer0.xdm
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pll_self_rst\syn\rev_1\pll_rst_ctrl.tlg
pll_self_rst\syn\rev_1\pll_rst_ctrl.vqm
pll_self_rst\syn\rev_1\pll_rst_ctrl_cons.tcl
pll_self_rst\syn\rev_1\pll_rst_ctrl_dsp.fdc
pll_self_rst\syn\rev_1\pll_rst_ctrl_rm.tcl
pll_self_rst\syn\rev_1\pll_rst_ctrl_scck.rpt
pll_self_rst\syn\rev_1\pll_rst_ctrl_synplify.fdc
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pll_self_rst\syn\rev_1\run_ise.tcl
pll_self_rst\syn\rev_1\run_options.txt
pll_self_rst\syn\rev_1\scratchproject.prs
pll_self_rst\syn\rev_1\synlog\pll_rst_ctrl_compiler.srr
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pll_self_rst\syn\rev_1\synlog\pll_rst_ctrl_premap.szr
pll_self_rst\syn\rev_1\synlog\report\pll_rst_ctrl_compiler_notes.txt
pll_self_rst\syn\rev_1\synlog\report\pll_rst_ctrl_compiler_runstatus.xml
pll_self_rst\syn\rev_1\synlog\report\pll_rst_ctrl_fpga_mapper_area_report.xml
pll_self_rst\syn\rev_1\synlog\report\pll_rst_ctrl_fpga_mapper_combined_clk.rpt
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pll_self_rst\syn\rev_1\synlog\report\pll_rst_ctrl_fpga_mapper_warnings.txt
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pll_self_rst\syn\rev_1\synlog\report\pll_rst_ctrl_premap_runstatus.xml
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pll_self_rst\syn\rev_1\synlog\syntax_constraint_check.rpt.rptmap
pll_self_rst\syn\rev_1\synplicity.ucf
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pll_self_rst\syn\rev_1\syntmp\cmdrec_premap.log
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pll_self_rst\syn\rev_1\syntmp\pll_rst_ctrl_cons_ui.tcl
pll_self_rst\syn\rev_1\syntmp\pll_rst_ctrl_flink.htm
pll_self_rst\syn\rev_1\syntmp\pll_rst_ctrl_srr.htm
pll_self_rst\syn\rev_1\syntmp\pll_rst_ctrl_toc.htm
pll_self_rst\syn\rev_1\syntmp\run_option.xml
pll_self_rst\syn\rev_1\syntmp\sap.log
pll_self_rst\syn\rev_1\syntmp\statusReport.html
pll_self_rst\syn\rev_1\synwork\.cckTransfer
pll_self_rst\syn\rev_1\synwork\layer0.fdep
pll_self_rst\syn\rev_1\synwork\layer0.fdepxmr
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